Patents by Inventor Antonio R. Alvarez

Antonio R. Alvarez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190260667
    Abstract: A system and method for validating proof of transit of network traffic through network nodes (N), the node (N) comprising a set of input interfaces (20) receiving incoming packets, a first module (A) to identify a matching route within a routing table (23) and storing means (22) to provide next modules (B, C, D) with two private keys if the packet is matched and/or the packet metadata includes OPoT information. The second module (B) decrypts the OPoT metadata using the first private key associated to the link of the node from which the incoming packets are received. The node (N) has SSS metadata to be processed by a third module (C) for the correct generation of cumulative validation parameters. When the SSS process is finished by the third module (C), the fourth module (D) re-encrypts the OPoT metadata using the second private key before packet forwarding to the subsequent node in the path through output interfaces (21).
    Type: Application
    Filed: February 17, 2019
    Publication date: August 22, 2019
    Applicant: Telefónica, S.A
    Inventors: Alejandro Aguado Martín, Vicente Martín Ayuso, Diego R. López, Antonio Pastor Perales, Víctor López Alvarez
  • Patent number: 4927775
    Abstract: An improved method of fabricating a high performance bipolar and MOS integrated circuit is provided. The method utilizes a single polysilicon layer, a self-aligned emitter-base structure, self-aligned silicide contacts, and silicon dioxide sidewall spacers to obtain reduced emitter and base resistance, reduced collector to base capacitance, greater switching speed, and a higher packing density. The method also has the advantage of being simple and compatible with a method of fabricating MOS devices which improves performance and yield.
    Type: Grant
    Filed: March 6, 1989
    Date of Patent: May 22, 1990
    Assignee: Motorola Inc.
    Inventors: Antonio R. Alvarez, James A. Kirchgessner
  • Patent number: 4803175
    Abstract: A method for making a bipolar semiconductor device having silicide contacts which is compatible with the processing steps used in the fabrication of MOS devices. The present invention includes the use of sidewall spacers to limit the self-aligned implants of the extrinsic base and the silicide contact. The device is annealed so that the diffusion of the polysilicon layer which forms the emitter may be controlled. Since the emitter size may be controlled, the emitter to base contact area may be reduced resulting in improved device performance.
    Type: Grant
    Filed: September 14, 1987
    Date of Patent: February 7, 1989
    Assignee: Motorola Inc.
    Inventors: Antonio R. Alvarez, James A. Kirchgessner
  • Patent number: 4735681
    Abstract: A method for the construction of self aligned submicron trenches by forming projecting ridges on a surface, forming a mask over the surface and then etching back the ridges to form gaps in the mask which act as guides for the etching of trenches in the substrate below.
    Type: Grant
    Filed: August 15, 1986
    Date of Patent: April 5, 1988
    Assignee: Motorola Inc.
    Inventor: Antonio R. Alvarez