Patents by Inventor Antony Davies

Antony Davies has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100197525
    Abstract: A device (1) for housing a scientific sample comprising at least one sample well (2) and an on-board buffering substance (3) wherein the onboard buffering substance (3) at least partly surrounds the sample well (2). The on-board buffering substance (3) may be in the form of a matrix, such as a gel-like matrix. The device (1) may further comprise an insulating means. Also described is a substance for use in culturing and/or assaying a sample whereby the substance provides atmospheric and thermal buffering. The invention further provides a lid for a single-well or multi-well sample plate, the lid being configured to facilitate delivery of a sample through the lid into a well, and for sealing the well. The lid comprises moveable portions (52, 53) that have at least one orifice (54, 57) formed through the moveable portions (52, 53) such that a conduit is formed by alignment of the orifices (54, 57) of both the lid portions (52, 53).
    Type: Application
    Filed: March 13, 2008
    Publication date: August 5, 2010
    Inventors: Antony Davies, Siobhan Mitchell, Dermot Kelleher, Yuri Volkov
  • Publication number: 20070225520
    Abstract: There is provided stereoselective route to a compound of formula I: wherein R represents H or an alkali metal, Ar1 represents 4-chlorophenyl and Ar2 represents 2,5-difluorophenyl.
    Type: Application
    Filed: February 16, 2005
    Publication date: September 27, 2007
    Inventors: Karel Brands, Sarah Brewer, Antony Davies, Ulf Dolling, Deborah Hammond, David Lieberman, Jeremy Scott
  • Patent number: 7003066
    Abstract: In one embodiment of the invention, a phase selection unit for generating a recovered clock signal (SCLK), a phase select signal generator generates a phase select signals in response to a FWD signal and a BWD signal from a digital filter. The digital filter asserts the FWD signal if the phase of a SDIN (serial digital input) signal leads the phase of the recovered clock signal, and asserts the BWD signal if the phase of the SDIN (serial digital input) signal lags the phase of the recovered clock signal. A multiplexer receives a number of given clock signals arranged in a predetermined phase order and outputs selected first and second output clock signals, each being one of the given clock signals. A phase interpolator receives the selected first and second output clock signals from the multiplexer to generate the recovered clock signal having a phase that is phase interpolated between the phases of the first and second output clock signals.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: February 21, 2006
    Assignee: Lattice Semiconductor Corporation
    Inventors: Antony Davies, Chienkuang Chen, Ling Wang
  • Patent number: 6993108
    Abstract: In a digital filter of a DPLL (digital phase locked loop) for minimizing the bit error rate for multiple communications protocols, a first reloadable register portion stores a TBW (total bandwidth) value programmed into the first reloadable register portion through a first port, and a second reloadable register portion stores a DBW (differential bandwidth) value programmed into the second reloadable register portion through a second port. An up—counter generates an UP—CNT value by counting up each UP signal pulse generated by a phase transition detector when a first phase of a SDIN (serial data input) signal leads a second phase of a current ACLK (recovered clock) signal. A down—counter generates a DOWN—CNT value by counting up each DOWN signal pulse generated by the phase transition detector when the first phase of the SDIN (serial data input) signal lags the second phase of the current ACLK (recovered clock) signal.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: January 31, 2006
    Assignee: Lattice Semiconductor Corporation
    Inventors: Kuang Chi, Ling Wang, Antony Davies
  • Publication number: 20050222456
    Abstract: A novel process for preparing cyclohexanones (1) is described. The products are useful as gamma-secretase in-hibitors, or as intermediates in the synthesis of other gamma-secretase inhibitors.
    Type: Application
    Filed: July 30, 2003
    Publication date: October 6, 2005
    Inventors: Karel Brands, Antony Davies, Paul Oakley, Jeremy Scott, Duncan Shaw, Martin Teall
  • Patent number: 6463457
    Abstract: A distributed computing platform using the idle computational processing power of a plurality of provider computers is disclosed. At least one networked server collects tasks from client computers, schedules and distributes the tasks to networked provider computers, and collects and returns results to client computers. A client API forms tasks and collects results. A compute engine operates on the provider computers to communicate with the server and execute tasks using idle computational power.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: October 8, 2002
    Assignee: Parabon Computation, Inc.
    Inventors: Steven L. Armentrout, James O'Connor, James Gannon, Brian Sletten, Sean Cier, Sarah Carlson, Antony Davies, Jonathan Davis, Greg DuPertuis, Scott McLoughlin