Patents by Inventor Anup Gangwar

Anup Gangwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10817627
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: October 27, 2020
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
  • Patent number: 10791045
    Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 29, 2020
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Zheng Xu, Anup Gangwar
  • Patent number: 10783286
    Abstract: The present disclosure provides a computer-based method and system for synthesizing a NoC. Physical data, device data, bridge data and traffic data are determined based on an input specification for the NoC. A virtual channel (VC) is assigned to each traffic flow. A head of line (HoL) conflict graph (HCG) is constructed based on the traffic data and the VC assignments. A color is assigned to each HCG node to minimize HoL conflicts. A traffic graph (TG) is constructed for each color based on the physical data, the bridge data, the traffic data and the HCG, and a candidate topology is generated for each color based on the respective TG. The candidate topology for each color is merged to create a merged candidate topology, and the routers within the merged candidate topology are merged to generate a final topology for the NoC.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 22, 2020
    Assignee: Arm Limited
    Inventors: Nitin Kumar Agarwal, Anup Gangwar, Honnahuggi Harinath Venkata Naga Ambica Prasad, Ravishankar Sreedharan
  • Publication number: 20200267073
    Abstract: Virtual channel assignment in a network is achieved by constructing a Traffic Conflict Graph (TCG) dependent upon a network interconnect topology. The TCG has vertices corresponding to traffic entries in a network specification and edges that connect pairs of vertices. An edge weight, dependent upon interconnect topology and traffic flow characteristics, is assigned to each edge. The vertices are colored using minimum or soft coloring and the virtual channels are mapped to the traffic entries, according to the resulting colors, to provide a virtual channel assignment. The TCG may be constructed by generating a vertex in the TCG to represent each traffic entry, assigning a traffic flow characteristic of a traffic entry to a corresponding vertex and generating an edge between first and second vertices when a number of ‘qualified’ common edges, across all routes for corresponding traffic entries, is greater than zero.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 20, 2020
    Applicant: Arm Limited
    Inventors: Nitin Kumar Agarwal, Zheng Xu, Anup Gangwar
  • Publication number: 20200246078
    Abstract: A computer process including receiving first patient bone data of a patient leg and foot in a first pose, the first pose comprising a position and orientation of the patient leg relative to the patient foot as defined in the first patient bone data. The computer process may further include receiving second patient bone data of the patient leg and foot in a second pose, the second pose comprising a position and orientation of the patient leg relative to the patient foot as defined in the second patient bone data. The computer process may further include generating a 3D bone model of the patient leg and foot. Finally, the computer process may include modifying the 3D bone model of the patient leg and foot such that the plurality of 3D bone models are reoriented into a third pose that matches the second pose.
    Type: Application
    Filed: April 23, 2020
    Publication date: August 6, 2020
    Applicant: Stryker European Holdings I, LLC
    Inventors: Ashish Gangwar, Kanishk Sethi, Anup Kumar, Ryan Sellman, Peter Sterrantino, Manoj Kumar Singh
  • Publication number: 20200179055
    Abstract: A method of generating a correction plan for correcting a deformed bone includes inputting to a computer system a first image of the deformed bone in a first plane and inputting to the computer system a second image of the deformed bone in a second plane. Image processing techniques are employed to identify a plurality of anatomical landmarks of the deformed bone in the first image. The first image of the deformed bone is displayed on a display device. A graphical of the deformed bone is autonomously generated and graphically overlaid on the first image of the deformed bone on the display device, the graphical template including a plurality of lines, each line connected at each end to a landmark point corresponding to one of the anatomical landmarks. A model of the deformed bone may be autonomously generated based on the graphical template.
    Type: Application
    Filed: February 18, 2020
    Publication date: June 11, 2020
    Inventors: Anup Kumar, Sridhar Anjanappa, Ashish Gangwar, Manash Lahiri, Arpit Gautam, Kanishk Sethi, Sistu Ganesh
  • Patent number: 10667867
    Abstract: A computer process including receiving first patient bone data of a patient leg and foot in a first pose, the first pose comprising a position and orientation of the patient leg relative to the patient foot as defined in the first patient bone data. The computer process may further include receiving second patient bone data of the patient leg and foot in a second pose, the second pose comprising a position and orientation of the patient leg relative to the patient foot as defined in the second patient bone data. The computer process may further include generating a 3D bone model of the patient leg and foot. Finally, the computer process may include modifying the 3D bone model of the patient leg and foot such that the plurality of 3D bone models are reoriented into a third pose that matches the second pose.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: June 2, 2020
    Assignee: Stryker European Holdings I, LLC
    Inventors: Ashish Gangwar, Kanishk Sethi, Anup Kumar, Ryan Sellman, Peter Sterrantino, Manoj Kumar Singh
  • Publication number: 20200134127
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han
    Type: Application
    Filed: October 25, 2018
    Publication date: April 30, 2020
    Inventors: Anup GANGWAR, Nitin Kumar AGARWAL, Honnahuggi Harinath Venkata Naga Ambica PRASAD
  • Patent number: 10635774
    Abstract: A computer-method is provided for designing a router network to connect components of an integrated circuit, where the router network comprises a plurality of connected data routing elements. The method comprises generating an undirected graph to represent a mesh of candidate router elements, where the candidate data routing elements are positioned dependent on at least one characteristic of the integrated circuit. The undirected graph comprises a node to represent each candidate data routing element and an edge to represent each connection between the candidate data routing elements.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: April 28, 2020
    Assignee: Arm Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal
  • Patent number: 10628626
    Abstract: A computer-implemented method of integrated circuit design comprises: using a computer, detecting data communication paths and associated data traffic requirements between a set of data handling nodes in an integrated circuit layout, the data handling nodes acting as routing nodes or either source nodes or sink nodes for a given data communication path, each source node and each sink node having a respective provisional data width, each data communication path having at least one routing node between the source node and the sink node; using the computer, assigning a provisional data width to each routing node so that, for each of the detected data communication paths, the one or more routing nodes in that data communication path have a provisional data width sufficient to handle the data traffic requirement associated with that communication path; using the computer, performing one or more iterations of modifying the integrated circuit topology by: (i) detecting two or more connected groups of the data han
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 21, 2020
    Assignee: Arm Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal, Honnahuggi Harinath Venkata Naga Ambica Prasad
  • Patent number: 10603112
    Abstract: A method of generating a correction plan for correcting a deformed bone includes inputting to a computer system a first image of the deformed bone in a first plane and inputting to the computer system a second image of the deformed bone in a second plane. Image processing techniques are employed to identify a plurality of anatomical landmarks of the deformed bone in the first image. The first image of the deformed bone is displayed on a display device. A graphical of the deformed bone is autonomously generated and graphically overlaid on the first image of the deformed bone on the display device, the graphical template including a plurality of lines, each line connected at each end to a landmark point corresponding to one of the anatomical landmarks. A model of the deformed bone may be autonomously generated based on the graphical template.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: March 31, 2020
    Assignee: Stryker European Holdings I, LLC
    Inventors: Anup Kumar, Sridhar Anjanappa, Ashish Gangwar, Manash Lahiri, Arpit Gautam, Kanishk Sethi, Sistu Ganesh
  • Publication number: 20190266308
    Abstract: A computer-method is provided for designing a router network to connect components of an integrated circuit, where the router network comprises a plurality of connected data routing elements. The method comprises generating an undirected graph to represent a mesh of candidate router elements, where the candidate data routing elements are positioned dependent on at least one characteristic of the integrated circuit. The undirected graph comprises a node to represent each candidate data routing element and an edge to represent each connection between the candidate data routing elements.
    Type: Application
    Filed: January 30, 2019
    Publication date: August 29, 2019
    Inventors: Anup GANGWAR, Nitin Kumar AGARWAL
  • Publication number: 20190183581
    Abstract: A method of generating a correction plan for correcting a deformed bone includes inputting to a computer system a first image of the deformed bone in a first plane and inputting to the computer system a second image of the deformed bone in a second plane. Image processing techniques are employed to identify a plurality of anatomical landmarks of the deformed bone in the first image. The first image of the deformed bone is displayed on a display device. A graphical of the deformed bone is autonomously generated and graphically overlaid on the first image of the deformed bone on the display device, the graphical template including a plurality of lines, each line connected at each end to a landmark point corresponding to one of the anatomical landmarks. A model of the deformed bone may be autonomously generated based on the graphical template.
    Type: Application
    Filed: February 27, 2019
    Publication date: June 20, 2019
    Inventors: Anup Kumar, Sridhar Anjanappa, Ashish Gangwar, Manash Lahiri, Arpit Gautam, Kanishk Sethi, Sistu Ganesh
  • Patent number: 10324509
    Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: June 18, 2019
    Inventors: Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar
  • Patent number: 10318243
    Abstract: A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 11, 2019
    Assignee: ARM Limited
    Inventors: Anup Gangwar, Nitin Kumar Agarwal
  • Publication number: 20190087157
    Abstract: A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains
    Type: Application
    Filed: September 21, 2017
    Publication date: March 21, 2019
    Inventors: Anup GANGWAR, Nitin Kumar AGARWAL
  • Patent number: 10042404
    Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: August 7, 2018
    Assignee: NETSPEED SYSTEMS
    Inventors: Anup Gangwar, Vishnu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar
  • Publication number: 20180181174
    Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Anup GANGWAR, Vishunu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar
  • Publication number: 20180181173
    Abstract: Systems and methods of the present disclosure relate to automatically and/or dynamically generating one or more power management sequences for SoC and NoC architectures from a given input specification having one or a combination of NoC design specification, traffic specification, traffic profile, power profile information, initiator-consumer relationship, interdependency between components, retention information, external factors, among other allied configurations/information to enable efficient switching of one or more hardware elements from one power profile to another.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Anup GANGWAR, Vishunu Mohan Pusuluri, Poonacha Kongetira, Sailesh Kumar
  • Patent number: 9829962
    Abstract: Aspects of the present disclosure relate to a method and system for hybrid and/or distributed implementation of generation and/or execution of power profile management instructions. An embodiment of the present disclosure provides a hardware element of a SoC/NoC that can be configured to generate and/or execute power profile management instructions using a hybrid combination of software and hardware, wherein the hardware element can be run in parallel with other hardware elements of the SoC/NoC to generate and execute power profile management instructions for different segments or regions of the SoC/NoC for efficient and safe working thereof.
    Type: Grant
    Filed: December 18, 2016
    Date of Patent: November 28, 2017
    Assignee: NetSpeed Systems, Inc.
    Inventors: Rimu Kaushal, Anup Gangwar, Vishnu Mohan Pusuluri, Sailesh Kumar