Patents by Inventor Anwar Ali

Anwar Ali has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070164451
    Abstract: A method for electrically coupling a bond pad of an integrated circuit such as a field programmable device, an application-specific integrated circuit, or a rapid chip with an input/output device is disclosed. The bond pad is provided with a plurality of metal layers configurable for making a connection with the input/output device. The bond pad is then coupled to the input/output device with an interconnect structure. The method for electrically coupling the bond pad to the input/output device allows the customer to configure the power and ground pad counts after the slice is created.
    Type: Application
    Filed: January 19, 2006
    Publication date: July 19, 2007
    Inventors: Anwar Ali, Tauman Lau, Kalyan Doddapaneni
  • Patent number: 7117467
    Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
    Type: Grant
    Filed: August 16, 2004
    Date of Patent: October 3, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Stan Mihelcic, James G. Monthie
  • Patent number: 7107561
    Abstract: A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: September 12, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Wei Huang
  • Patent number: 7075179
    Abstract: The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: July 11, 2006
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Julie L. Beatty, Kalyan Doddapaneni
  • Publication number: 20060131725
    Abstract: The present invention provides a system for implementing a configurable integrated circuit (IC). Aspects of the invention include an IC die; a plurality of input/outputs (I/Os) coupled to the IC die; and a plurality power planes coupled to the IC die for providing power to the plurality of I/Os at different voltages. The plurality of power planes are configured concentrically around the IC die so that any one or more of the I/Os at any location on the IC die can be individually configured to connect to any of the power planes. As a result, any number of I/Os available on the IC die can operate at a given voltage.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Publication number: 20060036987
    Abstract: The present invention is directed to methods for optimizing package and silicon co-design of an integrated circuit. A composite bump pattern for an integrated circuit is created based on a first library including at least one bump pattern template. PCB and Die constraints of the integrated circuit are then reviewed. A partial package design for the integrated circuit is generated based on a second library including at least one partial package template. A partial silicon design for said integrated circuit is started. A full package design for the integrated circuit is then completed. A full silicon design for the integrated circuit is completed.
    Type: Application
    Filed: August 16, 2004
    Publication date: February 16, 2006
    Inventors: Anwar Ali, Stan Mihelcic, James Monthie
  • Patent number: 6998638
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: February 14, 2006
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
  • Publication number: 20060027919
    Abstract: A method and computer program are disclosed for reducing routing congestion in an integrated circuit design that include steps of: (a) receiving as input a design for an integrated circuit die having an inner metal layer and a top metal layer wherein the design includes electrical constraints of each of a plurality of I/O circuits in the integrated circuit die; (b) selecting a number of vias for a via array to form an electrical connection between the inner metal layer and the top metal layer of the integrated circuit die that connects a solder bump formed on the top metal layer to a corresponding one of the plurality of I/O circuits wherein the number of vias is selected to satisfy the electrical constraints of the corresponding one of the plurality of I/O circuits; and (c) generating as output the number of vias determined for the via array.
    Type: Application
    Filed: August 9, 2004
    Publication date: February 9, 2006
    Inventors: Anwar Ali, Wei Huang
  • Publication number: 20060022687
    Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.
    Type: Application
    Filed: August 2, 2004
    Publication date: February 2, 2006
    Inventors: Anwar Ali, Julie Beatty, Kalyan Doddapaneni
  • Publication number: 20050125759
    Abstract: A computer-implemented method for creating slotted metal structures in a semiconductor design is disclosed. Aspects of the present invention include providing a library of different types of pre-slotted building block elements. Thereafter, during chip design, a plurality of the elements are selected from the library and placed in the design in abutment to form a composite slotted metal structure.
    Type: Application
    Filed: December 9, 2003
    Publication date: June 9, 2005
    Inventors: Anwar Ali, Tauman Lau, Kalyan Doddapaneni
  • Patent number: 6836026
    Abstract: Various integrated circuits (ICs) are provided. One IC includes bonding pads and an input output (I/O) region surrounding a core region. The I/O region includes I/O cells having a width approximately equal to or less than a width of the bonding pads. The IC also includes core logic arranged within the I/O region. Another IC includes four rows of bonding pads. Each row is arranged parallel to a different side of a core region. I/O sub-regions are arranged proximate each side of the core region. Each I/O sub-region includes I/O cells and core logic. An additional IC includes a first I/O region surrounding a core region and a second I/O region surrounding the first I/O region. The IC also includes bonding pads arranged outside of I/O cells in the first and second I/O regions. A width of the I/O cells is approximately equal to a pitch of the bonding pads.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: December 28, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Max M. Young
  • Patent number: 6815812
    Abstract: A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: November 9, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Ken Nguyen, Max M. Yeung
  • Publication number: 20040217487
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Application
    Filed: May 28, 2004
    Publication date: November 4, 2004
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
  • Patent number: 6798069
    Abstract: An integrated circuit is provided which includes at a first, a second, or a third row of bonding pads. A plurality of trace conductors is provided to route the signal of each bonding pad to an I/O ring and/or a core. The trace conductors of different metal widths are configured on a separate and distinct metal layers such that routing may be done above or below the bonding pad rows and other trace conductors. A plurality of vias is provided to connect between the different metal layers. This allows multiple rows of bonding pads to be arranged on the perimeters of the core without having to compromise for small pitch distances or longer routing paths.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: September 28, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Kalyan Doddapaneni
  • Patent number: 6784102
    Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: August 31, 2004
    Assignee: LSI Logic Corporation
    Inventors: Max M. Yeung, Tauman T. Lau, Anwar Ali
  • Patent number: 6781228
    Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: August 24, 2004
    Assignee: LSI Logic Corporation
    Inventors: Hiroshi Ishikawa, Thomas Antisseril, Radoslav Ratchkov, Bo Shen, Prasad Subbarao, Maad Al-Dabagh, Anwar Ali, Benjamin Mbouombouo
  • Patent number: 6781150
    Abstract: An integrated circuit having a crack detection structure. A control structure is formed having interleaved electrically conductive layers and non electrically conductive layers in a vertical orientation. Electrically conductive vias are disposed vertically through all of the non electrically conductive layers, which vias electrically connect all of the electrically conductive layers one to another. A test structure is formed having a bonding pad for probing and bonding, with underlying interleaved electrically conductive layers and non electrically conductive layers disposed in a vertical orientation. At least one of the non electrically conductive layers has no vias formed therein, simulating active circuitry under other bonding pads of the integrated circuit. At least one of the interleaved electrically conductive layers of the control structure extends from within the control structure to within the test structure as a sensing layer.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: August 24, 2004
    Assignee: LSI Logic Corporation
    Inventors: Qwai H. Low, Ramaswamy Ranganathan, Anwar Ali, Tauman T. Lau
  • Patent number: 6768142
    Abstract: A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs.
    Type: Grant
    Filed: May 8, 2002
    Date of Patent: July 27, 2004
    Assignee: LSI Logic Corporation
    Inventors: Anwar Ali, Tauman T. Lau, Max M. Yeung, Ken Nguyen, Wei Huang
  • Publication number: 20040135263
    Abstract: A multiple layer mesh design which includes a layer which provides a vertical mesh and an adjacent layer which provides a horizontal mesh which includes an open area or hole. The layer which provides the horizontal mesh (with hole) may either be above or below the vertical mesh layer, depending on the design. The vertical mesh may be full or may surround an open area or hole where the design includes both a horizontal donut mesh and a vertical donut mesh.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 15, 2004
    Inventors: Hiroshi Ishikawa, Thomas Antisseril, Radoslav Ratchkov, Bo Shen, Prasad Subbarao, Maad Al-Dabagh, Anwar Ali, Benjamin Mbouombouo
  • Publication number: 20040072421
    Abstract: A method of increasing mechanical interlocking between a first structure and a second adjacent structure in an integrated circuit. The first structure is formed with a first surface having a first horizontal component, and the second structure is formed with a second surface having a second horizontal component. The first surface laterally engages the second surface and the first horizontal component is complementary to the second horizontal component, such that the first structure prohibits vertical movement of the second structure.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 15, 2004
    Inventors: Max M. Yeung, Tauman T. Lau, Anwar Ali