Patents by Inventor Arash Farhoodfar
Arash Farhoodfar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240063940Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.Type: ApplicationFiled: October 26, 2023Publication date: February 22, 2024Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
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Patent number: 11909708Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.Type: GrantFiled: September 9, 2022Date of Patent: February 20, 2024Assignee: Marvell Asia Pte LtdInventors: Whay Sing Lee, Arash Farhoodfar
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Patent number: 11902721Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.Type: GrantFiled: March 2, 2022Date of Patent: February 13, 2024Assignee: MARVELL ASIA PTE LTDInventors: Whay Sing Lee, Arash Farhoodfar, Volodymyr Shvydun, Michael Duckering
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Patent number: 11888613Abstract: An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.Type: GrantFiled: February 3, 2022Date of Patent: January 30, 2024Assignee: MARVELL ASIA PTE LTDInventors: Benjamin Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
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Patent number: 11861190Abstract: Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions.Type: GrantFiled: April 8, 2021Date of Patent: January 2, 2024Assignee: Marvell Asia Pte, Ltd.Inventors: Arash Farhoodfar, Whay Lee
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Patent number: 11855702Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.Type: GrantFiled: February 17, 2022Date of Patent: December 26, 2023Assignee: MARVELL ASIA PTE LTDInventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
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Patent number: 11804925Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.Type: GrantFiled: March 14, 2022Date of Patent: October 31, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
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Publication number: 20230327806Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Inventors: Jamal RIANI, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
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Patent number: 11736596Abstract: An optical module includes first circuitry configured to receive data transmitted from a host over an electrical communication link at a first data rate, the data transmitted from the host being either one of PCIe data and CXL data and change a data rate for transmission of data from the optical module, the data transmitted from the optical module being transmitted at a second data rate different from the first data rate. Second circuitry is configured to convert the data transmitted from the host at the first data rate from an electrical format to an optical format for transmission from the optical module at the second data rate and convert data received from an optical receiver at the second data rate from the optical format to the electrical format for transmission from the optical module to the host at the first data rate via the first circuitry.Type: GrantFiled: July 1, 2022Date of Patent: August 22, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Kumaran David Siva, Arash Farhoodfar, Radhakrishnan L. Nagarajan
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Patent number: 11683124Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: GrantFiled: February 22, 2022Date of Patent: June 20, 2023Assignee: Marvell Asia Pte Ltd.Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Srinivas Swaminathan, Arash Farhoodfar
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Publication number: 20230185757Abstract: A multi-lane integrated circuit transceiver device includes first and second integrated circuit dies having respective first and second pluralities of transmit block/receive block pairs. Each respective transmit block and each respective receive block in the first plurality of block pairs on the first die and the second plurality of block pairs on the second die includes respective digital clock generation circuitry. The device further includes digital clock distribution circuitry to distribute a digital clock signal output by one respective receive block, in one of the first and second pluralities of block pairs, to the transmit blocks in both of the pluralities of block pairs, for use as a baseline clock by the respective digital clock generation circuitry in each of the transmit blocks in both of the pluralities of block pairs. Where each plurality includes N block pairs, the two dies together form a single 2N-lane device.Type: ApplicationFiled: December 8, 2022Publication date: June 15, 2023Inventors: Michael Lewis Takefman, Arash Farhoodfar, Srinivas Swaminathan, Belal Helal
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Patent number: 11616764Abstract: In an optical communication system, a high-speed data interface to an optical module can be configured from the module's host-side interface and line-side interface. These module interfaces can be configured with an integrated digital signal processor (DSP) having a DSP microcontroller unit (MCU) as a high-speed in-band DSP management interface. The DSP MCU can communicate to either a host MCU in a host switch/router via the host-side interface or to an external device through the optics hardware via the line-side interface. The present invention provides for systems, devices, and methods using this interface for numerous module DSP-related applications, such as firmware upgrades, management data, diagnostic/telemetry streaming, encryption key programming, and the like.Type: GrantFiled: December 30, 2019Date of Patent: March 28, 2023Assignee: MARVELL ASIA PTE LTD.Inventors: Todd Rope, Whay Sing Lee, Arash Farhoodfar
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Publication number: 20230055799Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.Type: ApplicationFiled: September 9, 2022Publication date: February 23, 2023Inventors: Whay Sing LEE, Arash Farhoodfar
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Publication number: 20220326864Abstract: Memory blocks are allocated for a microcontroller having one memory subsystem storing instruction information, and a separate memory subsystem storing data information. At design time, an address map is created implementing configurations of different ways of allocating instruction information and data information between memory blocks. At runtime, a configuration signal is received, and a particular memory block configuration for storing instruction information and data information is determined. An incoming instruction signal received from a dedicated microcontroller port, is communicated according to the configuration signal and the address map to a connection point (e.g., pin, fuse, register). Via that connection point, the instruction signal is routed to a memory block designated exclusively for instructions.Type: ApplicationFiled: April 8, 2021Publication date: October 13, 2022Inventors: Arash FARHOODFAR, Whay LEE
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Patent number: 11470038Abstract: The present invention is directed to data communication systems and techniques thereof. In a specific embodiment, the present invention provides a network connector that includes an interface for connecting to a host. The interface includes a circuit for utilizing two data paths for the host. The circuit is configured to transform the host address to different addresses based on the data path being used. There are other embodiments as well.Type: GrantFiled: May 19, 2020Date of Patent: October 11, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Whay Sing Lee, Arash Farhoodfar
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Patent number: 11405134Abstract: An optical module processes first FEC (Forward Error Correction) encoded data produced by a first FEC encoder. The optical module has a second FEC encoder for further coding a subset of the first FEC encoded data to produce second FEC encoded data. The optical module also has an optical modulator for modulating, based on a combination of the second FEC encoded data and a remaining portion of the first FEC encoded data that is not further coded, an optical signal for transmission over an optical channel. The second FEC encoder is an encoder for an FEC code that has a bit-level trellis representation with a number of states in any section of the bit-level trellis representation being less than or equal to 64 states. In this manner, the second FEC encoder has relatively low complexity (e.g. relatively low transistor count) that can reduce power consumption for the optical module.Type: GrantFiled: December 18, 2020Date of Patent: August 2, 2022Assignee: MARVELL ASIA PTE LTD.Inventors: Benjamin P. Smith, Arash Farhoodfar
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Publication number: 20220224997Abstract: A communication device is configured to receive data at a first data rate and to transmit the data at a second data rate that is greater than the first data rate. The communication device includes a plurality of communication pipelines and a multiplexer. Each communication pipeline is configured to receive a respective input data stream including first data blocks having a first format compatible for transmission at the first data rate, convert the first data blocks into second data blocks having a second format compatible for transmission at the second data rate, and provide an indication when one of the input data streams that is expected to be received is not received. The multiplexer is configured to receive the second data blocks from the communication pipelines and to generate an output data stream for transmission at the second data rate when one of the input data streams is not received.Type: ApplicationFiled: March 2, 2022Publication date: July 14, 2022Inventors: Whay Sing LEE, Arash FARHOODFAR, Volodymyr SHVYDUN, Michael DUCKERING
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Patent number: 11388268Abstract: A first processing unit for a computer server apparatus includes a first circuit configured to process a first type of data to be transmitted and received over a communication channel in accordance with a peripheral component interconnect express (PCIe) protocol, a second circuit configured to process a second type of data to be transmitted and received over the communication channel in accordance with a compute express link (CXL) protocol, and an optical communication interface configured to modulate the first type of data and the second type of data into a first signal in a PAM format to be transmitted over the communication channel to a second processing unit and receive, from the second processing unit over the communication channel, a second signal including either one of the first type of data and the second type of data modulated in the PAM format.Type: GrantFiled: January 30, 2020Date of Patent: July 12, 2022Assignee: Marvell Asia Pte Ltd.Inventors: Kumaran David Siva, Arash Farhoodfar, Radhakrishnan L. Nagarajan
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Publication number: 20220201225Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.Type: ApplicationFiled: March 14, 2022Publication date: June 23, 2022Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
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Publication number: 20220173833Abstract: A data transmission device includes a de-interleaver configured to receive, from a host device at a first data rate, a data stream including encoded data, de-interleave the data stream into a plurality of forward error correction (FEC) data streams, and output the plurality of FEC data streams at a second data rate less than the first data rate. Each of a plurality of interleavers is configured to interleave a respective one of the plurality of FEC data streams into an intermediate data stream including first data blocks and second data blocks. An encoder module configured to generate, for each of the intermediate data streams, FEC blocks including a first parity section and a first data section, the first parity section including a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section including the first data blocks and the second data blocks, and output the FEC blocks at the second data rate.Type: ApplicationFiled: February 22, 2022Publication date: June 2, 2022Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Srinivas SWAMINATHAN, Arash FARHOODFAR