Patents by Inventor Aravindan J. BUSI

Aravindan J. BUSI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170110205
    Abstract: Disclosed is an integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.
    Type: Application
    Filed: October 20, 2015
    Publication date: April 20, 2017
    Inventors: Aravindan J. Busi, Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette
  • Publication number: 20170018313
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Application
    Filed: July 15, 2015
    Publication date: January 19, 2017
    Inventors: Aravindan J. BUSI, John R. GOSS, Paul J. GRZYMKOWSKI, Krishnendu MONDAL, Kiran K. NARAYAN, Michael R. OUELLETTE, Michael A. ZIEGERHOFER
  • Publication number: 20160365156
    Abstract: Disclosed is a chip with a built-in self-test (BIST) circuit that incorporates a BIST engine that tests memories in parallel and that, prior to testing, dynamically sets the size of the address space to be swept. The BIST engine comprises an address generator that determines a superset of address space values associated with all the memories. This superset indicates the highest number of banks, the highest number of word lines per bank and the highest decode number for any of the memories. The address generator then generates test addresses and does so such that all test addresses are within a composite address space defined by the superset and, thereby within an address space that may, depending upon the memory configurations, be less than the predetermined maximum address space associated with such memories so as to reduce test time. Also disclosed is an associated BIST method for testing memories.
    Type: Application
    Filed: June 9, 2015
    Publication date: December 15, 2016
    Inventors: Aravindan J. Busi, Deepak I. Hanagandi, Krishnendu Mondal, Michael R. Ouellette
  • Patent number: 9514844
    Abstract: Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: December 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Aravindan J. Busi, Kevin W. Gorman, Kiran K. Narayan, Michael R. Ouellette
  • Publication number: 20160284426
    Abstract: A serial arbitration for memory diagnostics and methods thereof are provided. The method includes running a built-in-self-test (BIST) on a plurality of memories in parallel. The method further includes, upon detecting a failing memory of the plurality of memories, triggering arbitration logic to shift data of the failing memory to a chip pad.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Deepak I. HANAGANDI, Kiran K. NARAYAN, Michael R. OUELLETTE
  • Publication number: 20160064102
    Abstract: Logic and methods for diagnostic testing of memory and, more particularly, auto shift of failing memory diagnostics data using pattern detection are disclosed. The method includes detecting fails in the memory during a built in self test (BIST) pattern. The method further includes passing the fail information to a tester through a diagnostic pin. The method further includes pausing shift operations when it is determined that the shifting of the fail information is complete for the detected fail.
    Type: Application
    Filed: August 26, 2014
    Publication date: March 3, 2016
    Inventors: Aravindan J. BUSI, Kevin W. GORMAN, Kiran K. NARAYAN, Michael R. OUELLETTE