Patents by Inventor Aritoshi Sugimoto

Aritoshi Sugimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6780660
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: August 24, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6770496
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6771077
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Grant
    Filed: April 19, 2002
    Date of Patent: August 3, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Patent number: 6760472
    Abstract: A semiconductor substrate has a peculiar crystal defect. Crystal defects in a fixed area of a substrate can be treated as data acquired by coding the distribution of the crystal defects. The coded data is utilized for certificate data of an IC card by identifying a semiconductor substrate itself.
    Type: Grant
    Filed: December 10, 1999
    Date of Patent: July 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuo Takeda, Aritoshi Sugimoto, Takanori Ninomiya
  • Patent number: 6734687
    Abstract: Disconnection defects, short-circuit defects and the like in wiring patters of submicron sizes within TEGs (a square of 1 to 2.5 mm for each) numerously arranged in a large chip (a square of 20 to 25 mm) can be inspected with respect to all the TEGs, with good operability, high reliability and high efficiency. A conductor probe for applying voltage to the wiring patterns by mechanical contact is composed of synchronous type conductor probe that synchronizes with movement of a sample stage (16), and fixed type conductor probe means (21) that is relatively fixed to an FIB generator (10). Positions of probe tips are superimposed to an SIM image and displayed on a display unit (19).
    Type: Grant
    Filed: December 4, 2001
    Date of Patent: May 11, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems, Co., Ltd.
    Inventors: Tohru Ishitani, Hidemi Koike, Aritoshi Sugimoto, Isamu Sekihara, Kaoru Umemura, Satoshi Tomimatsu, Junzo Azuma
  • Patent number: 6717142
    Abstract: An inspection method and apparatus includes control of an acceleration voltage of an electron beam, irradiation of the electron beam to an object to be inspected mounted on a stage which is continuously moving at least in one direction, and detection of at least one of secondary electrons and reflected electrons emanated from the object in response to the irradiation. An image of the object is obtained from the detected electron by using positional information of the stage and inspection or measurement of the object is conducted using an obtained image. In the detection, an electric field in the vicinity of the object mounted on the stage is controlled so that at least one of the secondary electrons and the reflected electrons emanated from the object in response to the irradiation of the electron beam are decelerated.
    Type: Grant
    Filed: March 22, 2002
    Date of Patent: April 6, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Hiroi, Maki Tanaka, Masahiro Watanabe, Asahiro Kuni, Yukio Matsuyama, Yuji Takagi, Hiroyuki Shinada, Mari Nozoe, Aritoshi Sugimoto
  • Publication number: 20040047500
    Abstract: An apparatus for inspecting foreign matter in repeated micro-miniature patterns formed upon a surface of an object to be inspected, comprising: an inspection light illuminating device for irradiating an inspection light directed upon the surface of the object to be inspected, on which the repeated micro-miniature patterns are formed; a scattered light detector for detecting scattered light of the inspection light being scattered upon the surface said object to be inspected; means for obtaining a first information related to a foreign matter attaching upon the surface of said object to be inspected, which is obtained on a basis of the detection of said scattered light by said scattered light detector; an illumination means for applying a bright field illumination upon the surface of the object to be inspected, on which the repeated micro-miniature patterns are formed; means for picking up the image of the foreign matter, under a bright field illumination by said illumination means; means for obtaining a second
    Type: Application
    Filed: September 8, 2003
    Publication date: March 11, 2004
    Inventors: Junichi Taguchi, Aritoshi Sugimoto, Masami Ikoto, Yuko Inoue, Tetsuya Watanabe, Wakana Shinke
  • Patent number: 6703850
    Abstract: In order to obtain optimum irradiation conditions of an electron beam according to the material and structure of a circuit pattern to be inspected and the kind of a failure to be detected and inspect under the optimum conditions without delay of the inspection time, an inspection device for irradiating the electron beam 19 to the sample board 9 which is a sample, detecting generated secondary electrons by the detector 7, storing obtained signals sequentially in the storage, comparing the same pattern stored in the storage by the comparison calculation unit, and extracting a failure by comparing the predetermined threshold value with the comparison signal by the failure decision unit is provided, wherein the optimum value of the irradiation energy is stored in the data base inside the device beforehand according to the structure of a sample and a recommended value of the irradiation energy suited to inspection can be searched for by inputting or selecting the irradiation energy by a user or inputting informati
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: March 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Mari Nozoe, Hiroyuki Shinada, Kenji Watanabe, Keiichi Saiki, Aritoshi Sugimoto, Hiroshi Morioka, Maki Tanaka, Hiroshi Miyai
  • Patent number: 6661912
    Abstract: An apparatus for inspecting foreign matter in repeated micro-miniature patterns formed upon a surface of an object to be inspected, comprising: an inspection light illuminating device for irradiating an inspection light directed upon the surface of the object to be inspected, on which the repeated micro-miniature patterns are formed; a scattered light detector for detecting scattered light of the inspection light being scattered upon the surface said object to be inspected; means for obtaining a first information related to a foreign matter attaching upon the surface of said object to be inspected, which is obtained on a basis of the detection of said scattered light by said scattered light detector; an illumination means for applying a bright field illumination upon the surface of the object to be inspected, on which the repeated micro-miniature patterns are formed; means for picking up the image of the foreign matter, under a bright field illumination by said illumination means; means for obtaining a second
    Type: Grant
    Filed: August 3, 1998
    Date of Patent: December 9, 2003
    Assignee: Hitachi Electronics Engineering Co., Ltd.
    Inventors: Junichi Taguchi, Aritoshi Sugimoto, Masami Ikota, Yuko Inoue, Tetsuya Watanabe, Wakana Shinke
  • Publication number: 20030206027
    Abstract: In order to obtain optimum irradiation conditions of an electron beam according to the material and structure of a circuit pattern to be inspected and the kind of a failure to be detected and inspect under the optimum conditions without delay of the inspection time, an inspection device for irradiating the electron beam 19 to the sample board 9 which is a sample, detecting generated secondary electrons by the detector 7, storing obtained signals sequentially in the storage, comparing the same pattern stored in the storage by the comparison calculation unit, and extracting a failure by comparing the predetermined threshold value with the comparison signal by the failure decision unit is provided, wherein the optimum value of the irradiation energy is stored in the data base inside the device beforehand according to the structure of a sample and a recommended value of the irradiation energy suited to inspection can be searched for by inputting or selecting the irradiation energy by a user or inputting informati
    Type: Application
    Filed: May 7, 2003
    Publication date: November 6, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Mari Nozoe, Hiroyuki Shinada, Kenji Watanabe, Keiichi Saiki, Aritoshi Sugimoto, Hiroshi Morioka, Maki Tanaka, Hiroshi Miyai
  • Publication number: 20030199111
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030197522
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030199110
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
  • Publication number: 20030199107
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: April 19, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Kazuyuki Tsunokuni, Aritoshi Sugimoto
  • Publication number: 20030197523
    Abstract: A manufacturing method of an electronic device is to improve test efficiency using test structure and improve yield. The manufacturing method performs test using a first lead wire disposed on an insulating layer formed on a substrate and a second lead wire electrically connected to the substrate and disposed on the insulating layer and manages the electronic device on the basis of results of the test to manufacture the electronic device. The manufacturing method includes a step of testing whether the first lead wire is disconnected or not by measuring an electric resistance between both ends of the first lead wire and a step of testing whether the first and second lead wires are short-circuited or not by measuring an electric resistance between the first lead wire and the substrate.
    Type: Application
    Filed: October 10, 2002
    Publication date: October 23, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Yuichi Hamamura, Takaaki Kumazawa, Hisao Asakura, Aritoshi Sugimoto, Kazuyuki Tsunokuni
  • Publication number: 20030184332
    Abstract: A probe driving method and a probe apparatus for bringing a probe into contact with the surface of a sample in a safe and efficient manner by monitoring the probe height. Information about the height of the probe from the sample surface is obtained by detecting a probe shadow (54) appearing immediately before the probe contacts the sample, or based on a change in relative positions of a probe image and a sample image that are formed as an ion beam is irradiated diagonally.
    Type: Application
    Filed: November 29, 2002
    Publication date: October 2, 2003
    Inventors: Satoshi Tomimatsu, Hidemi Koike, Junzo Azuma, Tohru Ishitani, Aritoshi Sugimoto, Yuichi Hamamura, Isamu Sekihara, Akira Shimase
  • Publication number: 20030169060
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with the electron beam after a predetermined period of time from an instance when the electron beam is radiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Application
    Filed: March 6, 2003
    Publication date: September 11, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami
  • Patent number: 6583634
    Abstract: In order to obtain optimum irradiation conditions of an electron beam according to the material and structure of a circuit pattern to be inspected and the kind of a failure to be detected and inspect under the optimum conditions without delay of the inspection time, an inspection device for irradiating the electron beam 19 to the sample board 9 which is a sample, detecting generated secondary electrons by the detector 7, storing obtained signals sequentially in the storage, comparing the same pattern stored in the storage by the comparison calculation unit, and extracting a failure by comparing the predetermined threshold value with the comparison signal by the failure decision unit is provided, wherein the optimum value of the irradiation energy is stored in the data base inside the device beforehand according to the structure of a sample and a recommended value of the irradiation energy suited to inspection can be searched for by inputting or selecting the irradiation energy by a user or inputting informati
    Type: Grant
    Filed: April 27, 2000
    Date of Patent: June 24, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Mari Nozoe, Hiroyuki Shinada, Kenji Watanabe, Keiichi Saiki, Aritoshi Sugimoto, Hiroshi Morioka, Maki Tanaka, Hiroshi Miyai
  • Patent number: 6573546
    Abstract: A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Kiyonori Ohyu, Makoto Ohkura, Aritoshi Sugimoto, Yoshitaka Tadaki, Makoto Ogasawara, Masashi Horiguchi, Norio Hasegawa, Shinichi Fukada
  • Patent number: 6559663
    Abstract: A circuit pattern inspection method and an apparatus therefor, in which the whole of a portion to be inspected of a sample to be inspected is made to be in a predetermined charged state, the portion to be inspected is irradiated with an image-forming high-density electron beam while scanning the electron beam, secondary charged particles are detected at a portion irradiated with: the electron beam after a predetermined period of time from an instance when the electron beam is irradiated, an image is formed on the basis of the thus detected secondary charged particle signal, and the portion to be inspected is inspected by using the thus formed image.
    Type: Grant
    Filed: October 25, 2001
    Date of Patent: May 6, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Shinada, Mari Nozoe, Haruo Yoda, Kimiaki Ando, Katsuhiro Kuroda, Yutaka Kaneko, Maki Tanaka, Shunji Maeda, Hitoshi Kubota, Aritoshi Sugimoto, Katsuya Sugiyama, Atsuko Takafuji, Yusuke Yajima, Hiroshi Tooyama, Tadao Ino, Takashi Hiroi, Kazushi Yoshimura, Yasutsugu Usami