Patents by Inventor Arkalgud R. Sitaram

Arkalgud R. Sitaram has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9824974
    Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 21, 2017
    Assignee: INVENSAS CORPORATION
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Charles G. Woychik, Hong Shen, Arkalgud R. Sitaram, Liang Wang, Akash Agrawal, Rajesh Katkar
  • Publication number: 20170317019
    Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Applicant: INVENSAS CORPORATION
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Guilian Gao
  • Publication number: 20170309518
    Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
    Type: Application
    Filed: July 13, 2017
    Publication date: October 26, 2017
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
  • Publication number: 20170278787
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Application
    Filed: June 9, 2017
    Publication date: September 28, 2017
    Applicant: Invensas Corporation
    Inventors: Cyprian Emeka UZOH, Charles G. WOYCHIK, Arkalgud R. SITARAM, Hong SHEN, Zhuowen SUN, Liang WANG, Guilian GAO
  • Patent number: 9769923
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Patent number: 9741696
    Abstract: An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at least a first die and a second die interconnected to one another using die-to-die interconnects. A substrate of the first die has at least one thermal via structure extending from a lower surface of the substrate toward a well of the substrate without extending to the well and without extending through the substrate. A first end of the at least one thermal via structure is at least sufficiently proximate to the well of the substrate for conduction of heat away therefrom. The substrate has at least one through substrate via structure extending from the lower surface of the substrate to an upper surface of the substrate. A second end of the at least one thermal via structure is coupled to at least one through die via structure of the second die for thermal conductivity.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: August 22, 2017
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Arkalgud R. Sitaram, Cyprian Emeka Uzoh
  • Patent number: 9741620
    Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 22, 2017
    Assignee: INVENSAS CORPORATION
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Liang Wang, Hong Shen, Arkalgud R. Sitaram
  • Patent number: 9741649
    Abstract: An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a floor defining a front side surface. A plurality of first electroconductive contacts are disposed on the front side surface, and a plurality of second electroconductive contacts are disposed on the back side surface. A plurality of first electroconductive elements penetrate through the first substrate and couple selected ones of the first and second electroconductive contacts to each other. A first die containing an IC is electroconductively coupled to corresponding ones of the first electroconductive contacts. A second substrate has a bottom surface that is sealingly attached to the top surface of the first substrate, and a dielectric material is disposed in the cavity so as to encapsulate the first die.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: August 22, 2017
    Assignee: INVENSAS CORPORATION
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Guilian Gao
  • Patent number: 9691702
    Abstract: In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A, 120E.B) are provided above the substrate that wrap around the conductive vias' protrusions (114?) to form capacitors, electromagnetic shields, and possibly other elements. Other features and embodiments are also provided.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: June 27, 2017
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Charles G. Woychik, Arkalgud R. Sitaram, Hong Shen, Zhuowen Sun, Liang Wang, Guilian Gao
  • Patent number: 9685420
    Abstract: An apparatus relates generally to a microelectronic device. In such an apparatus, a first substrate has a first surface with first interconnects located on the first surface, and a second substrate has a second surface spaced apart from the first surface with a gap between the first surface and the second surface. Second interconnects are located on the second surface. Lower surfaces of the first interconnects and upper surfaces of the second interconnects are coupled to one another for electrical conductivity between the first substrate and the second substrate. A conductive collar is around sidewalls of the first and second interconnects, and a dielectric layer is around the conductive collar.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 20, 2017
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Cyprian Emeka Uzoh, Arkalgud R. Sitaram
  • Publication number: 20170099474
    Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels.
    Type: Application
    Filed: September 29, 2016
    Publication date: April 6, 2017
    Applicant: Invensas Corporation
    Inventors: Hong Shen, Liang Wang, Guilian Gao, Arkalgud R. Sitaram
  • Publication number: 20170099733
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Application
    Filed: December 15, 2016
    Publication date: April 6, 2017
    Applicant: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Publication number: 20170092620
    Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants K of the dielectric materials employed in the ultrathin layer and their respective thicknesses.
    Type: Application
    Filed: August 25, 2016
    Publication date: March 30, 2017
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Arkalgud R. Sitaram
  • Publication number: 20170084539
    Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Applicant: Invensas Corporation
    Inventors: Guilian GAO, Cyprian Emeka UZOH, Charles G. WOYCHIK, Hong SHEN, Arkalgud R. SITARAM, Liang WANG, Akash AGRAWAL, Rajesh KATKAR
  • Patent number: 9570385
    Abstract: Interposer circuitry (130) is formed on a possibly sacrificial substrate (210) from a porous core (130?) covered by a conductive coating (130?) which increases electrical conductance. The core is printed from nanoparticle ink. Then a support (120S) is formed, e.g. by molding, to mechanically stabilize the circuitry. A magnetic field can be used to stabilize the circuitry while the circuitry or the support are being formed. Other features are also provided.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: February 14, 2017
    Assignee: Invensas Corporation
    Inventors: Bong-Sub Lee, Cyprian Emeka Uzoh, Charles G. Woychik, Liang Wang, Laura Wills Mirkarimi, Arkalgud R. Sitaram
  • Publication number: 20170040237
    Abstract: Dies (110) with integrated circuits are attached to a wiring substrate (120), possibly an interposer, and are protected by a protective substrate (410) attached to a wiring substrate. The dies are located in cavities in the protective substrate (the dies may protrude out of the cavities). In some embodiments, each cavity surface puts pressure on the die to strengthen the mechanical attachment of the die the wiring substrate, to provide good thermal conductivity between the dies and the ambient (or a heat sink), to counteract the die warpage, and possibly reduce the vertical size. The protective substrate may or may not have its own circuitry connected to the dies or to the wiring substrate. Other features are also provided.
    Type: Application
    Filed: September 14, 2016
    Publication date: February 9, 2017
    Applicant: Invensas Corporation
    Inventors: Hong SHEN, Charles G. Woychik, Arkalgud R. Sitaram
  • Publication number: 20170040270
    Abstract: A method of processing an interconnection element can include providing a substrate element having front and rear opposite surfaces and electrically conductive structure, a first dielectric layer overlying the front surface and a plurality of conductive contacts at a first surface of the first dielectric layer, and a second dielectric layer overlying the rear surface and having a conductive element at a second surface of the second dielectric layer. The method can also include removing a portion of the second dielectric layer so as to reduce the thickness of the portion, and to provide a raised portion of the second dielectric layer having a first thickness and a lowered portion having a second thickness. The first thickness can be greater than the second thickness. At least a portion of the conductive element can be recessed below a height of the first thickness of the second dielectric layer.
    Type: Application
    Filed: August 6, 2015
    Publication date: February 9, 2017
    Inventors: Cyprian Emeka Uzoh, Guilian Gao, Bongsub Lee, Scott McGrath, Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram, Akash Agrawal
  • Publication number: 20170018517
    Abstract: Two microelectronic components (110, 120), e.g. a die and an interposer, are bonded to each other. One of the components' contact pads (110C) include metal, and the other component has silicon (410) which reacts with the metal to form metal silicide (504). Then a hole (510) is made through one of the components to reach the metal silicide and possibly even the unreacted metal (110C) of the other component. The hole is filled with a conductor (130), possibly metal, to provide a conductive via that can be electrically coupled to contact pads (120C.B) attachable to other circuit elements or microelectronic components, e.g. to a printed circuit board.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 19, 2017
    Applicant: Invensas Corporation
    Inventors: Hong SHEN, Liang WANG, Arkalgud R. SITARAM
  • Patent number: 9548273
    Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 17, 2017
    Assignee: Invensas Corporation
    Inventors: Guilian Gao, Cyprian Emeka Uzoh, Charles G. Woychik, Hong Shen, Arkalgud R. Sitaram, Liang Wang, Akash Agrawal, Rajesh Katkar
  • Patent number: 9536862
    Abstract: Semiconductor integrated circuits (110) or assemblies are disposed at least partially in cavities between two interposers (120). Conductive vias (204M) pass through at least one of the interposers or at least through the interposer's substrate, and reach a semiconductor integrated circuit or an assembly. Other conductive vias (204M.1) pass at least partially through multiple interposers and are connected to conductive vias that reach, or are capacitively coupled to, a semiconductor IC or an assembly. Other features are also provided.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 3, 2017
    Assignee: Invensas Corporation
    Inventors: Hong Shen, Charles G. Woychik, Arkalgud R. Sitaram