Abstract: In an embodiment, a method of fabricating a superjunction semiconductor device includes implanting first ions into a first region of a first epitaxial layer using a first implanting apparatus and nominal implant conditions to produce a first region in the first epitaxial layer comprising the first ions and a first implant characteristic and implanting second ions into a second region of the first epitaxial layer, the second region being laterally spaced apart from the first region, using second nominal implanting conditions estimated to produce a second region in the first epitaxial layer having the second ions and a second implant characteristic that lies within an acceptable maximum difference of the first implant characteristic.

Abstract: Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

Abstract: A semiconductor device includes a transistor cell area with active transistor cells including source zones electrically connected to a first load electrode. The source zones have a first conductivity type. An edge area surrounds the active transistor cell area and includes an edge construction that includes straight sections and a corner section connecting neighboring straight sections. A second dopant ratio between a mean concentration of dopants of a complementary second conductivity type and a mean concentration of dopants of the first conductivity type in the corner section exceeds a first dopant ratio between a mean concentration of dopants of the second conductivity type and a mean concentration of dopants of the first conductivity type in the straight sections by at least 0.2% in relation to the first dopant ratio.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Abstract: A transistor device includes drain, source and gate nodes, a plurality of drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type complementary to the first doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

Abstract: A semiconductor device includes a plurality of compensation regions arranged in a semiconductor substrate of the semiconductor device. The compensation regions of the plurality of compensation regions have a first conductivity type. The semiconductor device also includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement arranged in the semiconductor substrate of the semiconductor device. The drift region has a second conductivity type. Drift region portions of the plurality of drift region portions and compensation regions of the plurality of compensation regions are arranged alternatingly in a lateral direction. The semiconductor device further includes a tap electrode structure in contact with a tap portion of the drift region at a front side surface of the semiconductor substrate. The tap portion is located laterally between two neighboring compensation regions of the plurality of compensation regions.

Abstract: A semiconductor device includes an anode doping region of a diode structure arranged in a semiconductor substrate. The anode doping region has a first conductivity type. The semiconductor device further includes a second conductivity type contact doping region having a second conductivity type. The second conductivity type contact doping region is arranged at a surface of the semiconductor substrate and surrounded in the semiconductor substrate by the anode doping region. The anode doping region includes a buried non-depletable portion. At least part of the buried non-depletable portion is located below the second conductivity type contact doping region in the semiconductor substrate.

Abstract: A semiconductor device includes a plurality of compensation regions of a first conductivity type arranged in a semiconductor substrate. The semiconductor device further includes a plurality of drift region portions of a drift region of a vertical electrical element arrangement. The drift region has a second conductivity type. The drift region portions and the compensation regions are arranged alternatingly. At least portions of a border of a depletion region occurring in a static blocking state of the vertical electrical element arrangement are located within the drift region portions at a depth of less than a depth of at least a subset of the compensation regions.

Abstract: A super junction semiconductor device includes an impurity layer of a first (conductivity) type formed in a semiconductor portion having first and second parallel surfaces, a super junction structure between the first surface and impurity layer and including first columns of the first type and second columns of a second (conductivity) type, a body zone of the second type formed between the first surface and one of the second columns at least partially in the vertical projection of the second columns, and a field extension zone of the second type electrically connected to the body zone and arranged in the vertical projection of one of the columns. An area impurity density in the field extension zone is between 1×1012 and 5×1012 cm?2. A mean net impurity concentration in the field extension zone is higher than in the second columns and lower than in the body zone.

Abstract: A super junction semiconductor device includes a semiconductor portion with first and second surfaces parallel to one another and including a doped layer of a first conductivity type formed at least in a cell area. Columnar first super junction regions of a second conductivity type extend in a direction perpendicular to the first surface and are separated by columnar second super junction regions of the first conductivity type. The first and second super junction regions form a super junction structure between the first surface and the doped layer. A first electrode structure directly adjoins the first surface and a second electrode structure directly adjoins the second surface. The first electrode structure has a first thickness and the second electrode structure has a second thickness. A sum of the first and second thicknesses is at least 20% of the thickness of the semiconductor portion between the first and second surfaces.

Abstract: A trench transistor having a semiconductor body includes a source region, a body region, a drain region electrically connected to a drain contact, and a gate trench including a gate electrode which is isolated from the semiconductor body. The gate electrode is configured to control current flow between the source region and the drain region along at least a first side wall of the gate trench. The trench transistor further includes a doped semiconductor region having dopants introduced into the semiconductor body through an unmasked part of the walls of a trench.

Abstract: A semiconductor device includes a transistor cell area with active transistor cells including source zones electrically connected to a first load electrode. The source zones have a first conductivity type. An edge area surrounds the active transistor cell area and includes an edge construction that includes straight sections and a corner section connecting neighboring straight sections. A second dopant ratio between a mean concentration of dopants of a complementary second conductivity type and a mean concentration of dopants of the first conductivity type in the corner section exceeds a first dopant ratio between a mean concentration of dopants of the second conductivity type and a mean concentration of dopants of the first conductivity type in the straight sections by at least 0.2% in relation to the first dopant ratio.

Abstract: A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells and the outer rim. Each of the switchable cells includes a gate electrode structure. The semiconductor device further includes a gate metallization in contact with the gate electrode structure. The active area includes at least a first switchable region having a first specific transconductance and at least a second switchable region having a second specific transconductance which is different from the first specific transconductance. The second switchable region is arranged between the gate metallization and the first switchable region. A ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

Abstract: Disclosed is a transistor device. The transistor device includes: a semiconductor body with an active region and a pad region; at least one transistor cell including a gate electrode dielectrically insulated from a body region by a gate dielectric, wherein the body region is arranged in the active region; an electrode layer arranged above the pad region and dielectrically insulated from the pad region by a further dielectric; and a gate pad arranged above the electrode layer and electrically connected to the electrode layer and the gate electrode of the at least one transistor cell. A thickness of the further dielectric is equal to or less than a thickness of the gate dielectric.

Abstract: In a field-effect semiconductor device, alternating first n-type and p-type pillar regions are arranged in the active area. The first n-type pillar regions are in Ohmic contact with the drain metallization. The first p-type pillar regions are in Ohmic contact with the source metallization. An integrated dopant concentration of the first n-type pillar regions substantially matches that of the first p-type pillar regions. A second p-type pillar region is in Ohmic contact with the source metallization, arranged in the peripheral area and has an integrated dopant concentration smaller than that of the first p-type pillar regions divided by a number of the first p-type pillar regions. A second n-type pillar region is arranged between the second p-type pillar region and the first p-type pillar regions, and has an integrated dopant concentration smaller than that of the first n-type pillar regions divided by a number of the first n-type pillar regions.

Abstract: A super junction semiconductor device includes a semiconductor portion having strip structures in a cell area. Each strip structure has a compensation structure with first and second sections inversely provided on opposite sides of a fill structure. Each section has first and second compensation layers of complementary conductivity types. The strip structures are linear stripes extending through the cell area in a first lateral direction and into an edge area surrounding the cell area in lateral directions. Each strip structure has an end section with a termination portion in the edge area in which the first compensation layer of the first section is connected with the first compensation layer of the second section via a first conductivity layer, and the second compensation layer of the first section is connected with the second compensation layer of the second section via a second conductivity layer.

Abstract: The present disclosure provides a semiconductor device, which includes a compensation area which includes p-regions and n-regions, and a plurality of transistor cells on the compensation area. Each of the plurality of transistor cells includes a source region, a body region, a gate and an interlayer dielectric, and a source metallization layer arranged on the interlayer dielectric. The semiconductor device further includes an additional n-doping region that is provided on top of the n-regions between two neighboring body regions, and a source plug which fills a contact hole formed through the interlayer dielectric between the source and body region and the source metallization layer, so as to electrically connect the source and body region and the source metallization layer.

Abstract: A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.