Patents by Inventor Arnaud Regnier

Arnaud Regnier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9224482
    Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: December 29, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Julien Delalleau
  • Publication number: 20150348640
    Abstract: The present disclosure relates to a non-volatile memory cell on a semiconductor substrate, comprising a first transistor comprising a control gate, a floating gate and a drain region, a second transistor comprising a control gate, a floating gate and a drain region, in which the floating gates of the first and second transistors are electrically coupled, and the second transistor comprises a conducting region electrically coupled to its drain region and extending opposite its floating gate through a tunnel dielectric layer.
    Type: Application
    Filed: May 28, 2015
    Publication date: December 3, 2015
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20150348981
    Abstract: The present disclosure relates to a non-volatile memory on a semiconductor substrate, comprising: a first memory cell comprising a floating-gate transistor and a select transistor having an embedded vertical control gate, a second memory cell comprising a floating-gate transistor and a select transistor having the same control gate as the select transistor of the first memory cell, a first bit line coupled to the floating-gate transistor of the first memory cell, and a second bit line coupled to the floating-gate transistor of the second memory cell.
    Type: Application
    Filed: March 27, 2015
    Publication date: December 3, 2015
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20150348635
    Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.
    Type: Application
    Filed: May 22, 2015
    Publication date: December 3, 2015
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier
  • Publication number: 20150325581
    Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.
    Type: Application
    Filed: July 22, 2015
    Publication date: November 12, 2015
    Inventors: Arnaud Regnier, Stephan Niel, Francesco La Rosa
  • Publication number: 20150236031
    Abstract: The present disclosure relates to a memory cell that includes a vertical selection gate, a floating gate extending above the substrate, wherein the floating gate also extends above a portion of the vertical selection gate, over a non-zero overlap distance, the memory cell comprising a doped region implanted at the intersection of a vertical channel region extending opposite the selection gate and a horizontal channel region extending opposite the floating gate.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Inventors: Marc MANTELLI, Stephan NIEL, Arnaud REGNIER, Francesco LA ROSA, Julien DELALLEAU
  • Patent number: 9076878
    Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 7, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Yoann Goasduff
  • Publication number: 20150117117
    Abstract: The present disclosure relates to a memory cell comprising a vertical selection gate extending in a trench made in a substrate, a floating gate extending above the substrate, and a horizontal control gate extending above the floating gate, wherein the floating gate also extends above a portion of the vertical selection gate over a non-zero overlap distance. Application mainly to the production of a split gate memory cell programmable by hot-electron injection.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Francesco La Rosa, Stephan Niel, Julien Delalleau, Arnaud Regnier
  • Publication number: 20150117109
    Abstract: The present disclosure relates to a memory comprising at least one word line comprising a row of split gate memory cells each comprising a selection transistor section comprising a selection gate and a floating-gate transistor section comprising a floating gate and a control gate. According to the present disclosure, the memory comprises a source plane common to the memory cells of the word line, to collect programming currents passing through memory cells during their programming, and the selection transistor sections of the memory cells are connected to the source plane. A programming current control circuit is configured to control the programming current passing through the memory cells by acting on a selection voltage applied to a selection line.
    Type: Application
    Filed: October 30, 2014
    Publication date: April 30, 2015
    Inventors: Francesco LA ROSA, Stephan NIEL, Arnaud REGNIER, Julien DELALLEAU
  • Patent number: 9012961
    Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: April 21, 2015
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Hélène Dalle-Houilliez
  • Patent number: 8901634
    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: December 2, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Yoann Goasduff, Stephan Niel, Arnaud Regnier
  • Patent number: 8830761
    Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: September 9, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
  • Publication number: 20140246720
    Abstract: An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Inventors: Arnaud Regnier, Stephan Niel, Francesco La Rosa
  • Publication number: 20140191291
    Abstract: The disclosure relates to a method of manufacturing vertical gate transistors in a semiconductor substrate, comprising implanting, in the depth of the substrate, a doped isolation layer, to form a source region of the transistors; forming, in the substrate, parallel trench isolations and second trenches perpendicular to the trench isolations, reaching the isolation layer, and isolated from the substrate by a first dielectric layer; depositing a first conductive layer on the surface of the substrate and in the second trenches; etching the first conductive layer to form the vertical gates of the transistors, and vertical gate connection pads between the extremity of the vertical gates and an edge of the substrate, while keeping a continuity zone in the first conductive layer between each connection pad and a vertical gate; and implanting doped regions on each side of the second trenches, to form drain regions of the transistors.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 10, 2014
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Hélène Dalle-Houilliez
  • Patent number: 8729668
    Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Arnaud Regnier
  • Publication number: 20140097481
    Abstract: The present disclosure relates to a method for manufacturing a non-volatile memory on a semiconductive substrate, comprising the steps of implanting in the depth of the substrate a first doped region forming a source region of selection transistors, forming in the substrate a buried gate comprising deep parts extending between an upper face of the substrate and the first doped region, implanting between two adjacent deep parts of the buried gate, a second doped region forming a common drain region of common selection transistors of a pair of memory cells, the selection transistors of the pair of memory cells thus having channel regions extending between the first doped region and the second doped region, along faces opposite the two buried gate adjacent deep parts, and implanting along opposite upper edges of the buried gate, third doped regions forming source regions of charge accumulation transistors.
    Type: Application
    Filed: October 1, 2013
    Publication date: April 10, 2014
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Francesco La Rosa, Stephan Niel, Arnaud Regnier, Yoann Goasduff
  • Publication number: 20130229875
    Abstract: The disclosure relates to a method of reading and writing memory cells, each including a charge accumulation transistor in series with selection transistor, including applying a selection voltage to a gate of the selection transistor of the memory cell; applying a read voltage to a control gate of the charge accumulation transistor of the memory cell; applying the selection voltage to a gate of the selection transistor of a second memory cell coupled to the same bitline; and applying an inhibition voltage to a control gate of the charge accumulation transistor of the second memory cell, to maintain the transistor in a blocked state.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 5, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco La Rosa, Olivier Pizzuto, Stephan Niel, Philippe Boivin, Pascal Fornara, Laurent Lopez, Arnaud Regnier
  • Publication number: 20130228846
    Abstract: The disclosure relates to an integrated circuit comprising at least two memory cells formed in a semiconductor substrate, and a buried gate common to the selection transistors of the memory cells. The buried gate has a first section of a first depth extending in front of vertical channel regions of the selection transistors, and at least a second section of a second depth greater than the first depth penetrating into a buried source line. The lower side of the buried gate is bordered by a doped region forming a source region of the selection transistors and reaching the buried source line at the level where the second section of the buried gate penetrates into the buried source line, whereby the source region is coupled to the buried source line.
    Type: Application
    Filed: March 5, 2013
    Publication date: September 5, 2013
    Applicant: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Francesco LA ROSA, Yoann GOASDUFF, Stephan NIEL, Arnaud REGNIER
  • Publication number: 20130032926
    Abstract: An adjustable resistor formed on a first insulating layer of a substrate, including: a first polysilicon layer covered with a second insulating layer of a first thickness, except in a region where the first polysilicon layer is covered with a thin insulator layer of a second thickness smaller than the first thickness; a second polysilicon layer covering the second insulating layer and the thin insulator layer; on each side of the second insulating layer and at a distance from it, a first and a second conductive vias providing access to the terminals of the resistor on the first polysilicon layer; and a third conductive via providing access to a contacting area on the second polysilicon layer.
    Type: Application
    Filed: July 19, 2012
    Publication date: February 7, 2013
    Inventors: Pascal FORNARA, Arnaud Regnier
  • Patent number: 7675106
    Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: March 9, 2010
    Assignees: STMicroelectronics S.A., STMicroelectronics SAS, France Universite d'Aix-Marseille
    Inventors: Rachid Bouchakour, Virginie Bidal, Philippe Candelier, Richard Fournel, Philippe Gendrier, Romain Laffont, Pascal Masson, Jean-Michel Mirabel, Arnaud Regnier