Abstract: A flash-memory-card reader reads and writes multiple types of flash-memory cards, including CompactFlash, and the smaller SmartMedia, MultiMediaCard, Secure Digital, and Memory Stick. A converter chip converts the different card signals for transfer to a host personal computer (PC). Serial-to-parallel data conversion is performed for the smaller card formats with serial data interfaces, but not for CompactFlash with a parallel-data interface. A single slot has a 50-pin connector for CompactFlash cards or passive adapters. The passive adapters have the CompactFlash form factor and a smaller connector fitting smaller flash cards. Passive adapters have no components but simply wire the smaller connector to the CompactFlash connector. A pin mapping allows card-type detection by sensing the LSB address pins of the CompactFlash interface. A larger CompactFlash reader has multiple slots for each card type. The reader is connected to the PC by a cable, or located within the PC chassis in a drive bay.

Abstract: A flash-memory-card reader reads and writes multiple types of flash-memory cards, including CompactFlash, and the smaller SmartMedia, MultiMediaCard, Secure Digital, and Memory Stick. A converter chip converts the different card signals for transfer to a host personal computer (PC). Serial-to-parallel data conversion is performed for the smaller card formats with serial data interfaces, but not for CompactFlash with a parallel-data interface. A single slot has a 50-pin connector for CompactFlash cards or passive adapters. The passive adapters have the CompactFlash form factor and a smaller connector fitting smaller flash cards. Passive adapters have no components but simply wire the smaller connector to the CompactFlash connector. A pin mapping allows card-type detection by sensing the LSB address pins of the CompactFlash interface. A larger CompactFlash reader has multiple slots for each card type. The reader is connected to the PC by a cable, or located within the PC chassis in a drive bay.

Abstract: An external mass storage device is secured against unauthorized access. A fingerprint reader is integrated on the external mass storage device. An initialization routine is executed when the device is plugged into a personal computer (PC) using a USB, IEEE 1394, PCMCIA, or other interface. The initialization routine scans the user's fingerprint and extracts biometric information. The biometric information is compared to stored biometric records to determine if the user is authorized to access the external mass storage device. When authorization fails, the initialization routine halts, preventing the PC from mounting the external mass storage, thus blocking access. When authentication passes, initialization continues and the external mass storage is mounted and accessible from the PC. Since the initialization routine and stored biometric records are stored on the external mass storage, the external mass storage is protected even when moved to a different PC.

Abstract: An external hard disk is connected to a personal computer (PC) through the parallel port. A parallel-port expansion card is installed on the AT bus in the PC for communicating with the external hard disk. The parallel-port expansion card has a ROM containing intercept code. The address of the ROM is automatically configured when the system BIOS scans for expansion ROMs during booting. When no other ROM drives the data bus when an address is scanned, the parallel-port card latches the address and has the ROM drive its data onto the bus. Future accesses to the latched address access the ROM. The ROM's code replaces the interrupt table's starting address of the hard-disk-controller routine with the address of an intercept routine. All hard-disk operations using the interrupt first execute the intercept routine. The intercept routine copies any data writes to the external disk. Thus the external disk has a redundant copy of the PC's internal hard disk.

Abstract: The timing of control signals in a parallel port is measured and adjusted to achieve optimum timing of these control signals. At boot-up, a routine writes alternating data to the control register of the parallel port. The control register drives control signal over a parallel-port cable to an external parallel-port device connected to the parallel port of a personal computer (PC). Transitions of the control signal trigger an external timer in the external parallel-port device which measures the pulse width of the control signal. The measured pulse width is sent back to the PC over the parallel cable and compared to a target pulse width. When the measured pulse width is less than the target, additional intervening instructions are inserted between writes to the parallel-port control register. The intervening instructions are a simple delay loop. Alternately the internal timer on the PC may be used. Since the accuracy is less for the internal timer, many IO writes are performed to average out errors.

Abstract: A front-panel display of a PC has several 7-segment light-emitting diode (LED) displays. A serial link is provided from an I/O port on the PC motherboard to the front panel display. This serial link uses the turbo-in line that is normally used to light the turbo LED indicator. A microcontroller on the front-panel display samples the turbo-in line and extracts serial data once a start sequence is detected. The serial data is converted to parallel form, and then encoded into a code that can be decoded by the 7-segment LED displays. The microcontroller drives this code to the 7-segment displays so that the serial data from the I/O port on the PC motherboard is displayed by the 7-segment displays on the front panel. Software on the PC periodically writes to the I/O port to update the data bit transmitted. This software can thus alter the front panel display. Information displayed on the front panel can include the temperature of the CPU or power reduction in suspend modes.

Abstract: A logic device having a state machine for serially transferring data between an AT-compatible mother board and a keyboard having a microcontroller for scanning the keyboard matrix, without the need for a microcontroller on the mother board. A timer is provided to signal a transmission time-out error, and to indicate the start delay before beginning to transfer data when transmitting to the keyboard. Transmission to the keyboard begins by asserting the clock and serial data bit to the keyboard, and waiting for the start delay to expire. The state machine has a chain of 22 states for transferring an 11-bit data frame, the state transitions occurring after the clock from the keyboard or mouse changes polarity. A time-out error state is entered if a timer indicates that a 32 ms period of time has elapsed. Both transmit and receive operations may time-out with the same delay, and enter the same error state.

Abstract: A parity generating circuit that can replace the parity bit DRAM on a 9-bit SIMM. The parity generating circuit includes a parity generating tree which outputs the resulting even parity from the 8 data bits on a read. A 9th data input from another parity generator on the system mother board is compared to the generator tree output when DRAM is written to. If a mismatch occurs, the type of parity generated by the generator tree is opposite to the type of parity that the mother board generates, and the parity tree output must be inverted on subsequent reads. A latch is provided to store the compare result, which also indicates the type of parity required, even or odd, on the particular system the SIMM is installed on. The latch is loaded when the DRAM is written to. The state of the latch is used to output the correct type of parity on a read from DRAM by inverting the output of the parity generating circuit if needed.