Patents by Inventor Arthur L. Swift, IV

Arthur L. Swift, IV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5081375
    Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.
    Type: Grant
    Filed: January 2, 1991
    Date of Patent: January 14, 1992
    Assignee: National Semiconductor Corp.
    Inventors: Scott K. Pickett, Thomas M. Luich, Arthur L. Swift, IV
  • Patent number: 5021689
    Abstract: A PLA is formed using configurable logic elements. A plurality of pages are used to store information defining logic configuration patterns required to perform desired logical functions. The configurable logic elements are configured by downloading information from a desired one or more of said pages. If desired, page control is achieved in response to input signals to the configurable logic array.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: June 4, 1991
    Assignee: National Semiconductor Corp.
    Inventors: Scott K. Pickett, Thomas M. Luich, Arthur L. Swift, IV
  • Patent number: 4942319
    Abstract: A PLA is organized into a plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages of programmable logic arrays, including means for selecting an appropriate set of one or more of the plurality of pages for operation at any given time. Means are provided for switching pages when necessary in response to input signals including, if desired, signals fed back from the output leads of the PLA, or internal leads within the PLA. By having only a selected one or more of the pages of the PLA operable at any given time, the number of product and sum terms functioning at any given time is significantly less than the total number of product and sum terms available in the device, thereby minimizing power consumption. Furthermore, by utilizing a paged architecture, speed is increased and power consumption reduced since the number of leads connected to, and thus the capacitance of, the product and/or sum term lines is reduced.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: July 17, 1990
    Assignee: National Semiconductor Corp.
    Inventors: Scott K. Pickett, Thomas M. Luich, Arthur L. Swift, IV