Abstract: A method includes the steps of differentiating Overlays each into a code portion and into a data portion, storing the data portions within a CPU directly-accessible memory, storing the code portions within a memory not-directly accessible by the CPU, and swapping a required code portion into the directly-accessible memory for execution by the CPU such that the swapped-in code portion has access to a plurality of the data portions stored within the directly-accessible memory.

Abstract: A method is described for transferring data units from a serially organized memory to a bit planar organized memory. The method first selects a plurality of data units from the serially organized memory. A bit pattern from the selected data units is then captured, which bit pattern includes only bits to be stored in a subset of the storage planes of the bit planar organized memory. The bit pattern is processed to isolate from it, subsidiary bit patterns, one bit pattern for each storage plane in the bit planar memory. Each subsidiary bit pattern is then translated so that its bit sequence is properly oriented and is then stored in a plane of the bit planar organized memory. In a preferred embodiment of the invention, the translations take place as the result of a table look-up step.

Abstract: A method for synchronizing common values in a distributed system, at least one node of which is a cyclic, rule-based, object-sensitive production system. Values altered in one part of the system are implicity rather than explicitly communicated and processed to and from the rule-based node. All communications to the rule-based node of common values changed by the nonrule-based nodes are by way of a list independent of and concurrently with any procedural request of the rule-based node, there being no necessary relation between the list contents and the procedural request.

Abstract: A graphic display PC/interface system is described which includes three memory units: a source memory which is addressed in planar byte increments and stores display data units on a bit per plane basis; a target memory for storing display data units in a manner suitable for operation of a display unit; and a window buffer for transferring display data unit from the source memory to the target memory. The system transfers a quantity of display data unit bytes from the source memory to the target memory by accessing pairs of planar bytes, which pair of planar bytes may have a display data unit byte bridging therebetween.