Patents by Inventor Artto Aurola
Artto Aurola has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220166432Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: ApplicationFiled: February 8, 2022Publication date: May 26, 2022Inventor: Artto AUROLA
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Patent number: 11283450Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: GrantFiled: November 24, 2020Date of Patent: March 22, 2022Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Publication number: 20210083667Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: ApplicationFiled: November 24, 2020Publication date: March 18, 2021Inventor: Artto AUROLA
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Publication number: 20200411517Abstract: Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.Type: ApplicationFiled: September 9, 2020Publication date: December 31, 2020Inventor: Artto Aurola
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Patent number: 10879900Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: GrantFiled: June 20, 2019Date of Patent: December 29, 2020Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Patent number: 10833080Abstract: Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.Type: GrantFiled: July 13, 2017Date of Patent: November 10, 2020Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Publication number: 20190319625Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: ApplicationFiled: June 20, 2019Publication date: October 17, 2019Inventor: Artto AUROLA
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Patent number: 10389360Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: GrantFiled: October 29, 2018Date of Patent: August 20, 2019Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Publication number: 20190244958Abstract: Disclosed is a semiconductor logic element having a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries with the described logic element.Type: ApplicationFiled: July 13, 2017Publication date: August 8, 2019Inventor: Artto AUROLA
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Patent number: 10243565Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: GrantFiled: April 16, 2018Date of Patent: March 26, 2019Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Publication number: 20190074837Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: ApplicationFiled: October 29, 2018Publication date: March 7, 2019Inventor: Artto AUROLA
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Patent number: 10079325Abstract: A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a MIG layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor. The device further includes a first conductivity type first contact, so that the pixel voltage is a potential difference between one of the pixel dopings and the first conductivity type first contact. The location of a main gate (983) corresponds at least partly to the location of a channel between the source and the drain. The device includes at least one extra gate (981, 982) horizontally displaced from the main gate (983).Type: GrantFiled: November 4, 2014Date of Patent: September 18, 2018Inventor: Artto Aurola
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Publication number: 20180241397Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: ApplicationFiled: April 16, 2018Publication date: August 23, 2018Inventor: Artto AUROLA
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Patent number: 9948304Abstract: Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.Type: GrantFiled: January 13, 2016Date of Patent: April 17, 2018Assignee: HYPERION SEMICONDUCTORS OYInventor: Artto Aurola
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Publication number: 20160340215Abstract: The invention relates to a method for processing sulphate-containing water. The method contains stages in which sulphate-containing water is directed to an anaerobic bioreactor, and an anaerobic bacterial strain that converts sulphate to hydrogen sulphide converts the sulphate contained in the water to hydrogen sulphide gas. The resulting hydrogen sulphide gas is directed for incineration in a hydrogen sulphide incineration unit, which produces combustion gases containing sulphur dioxide. Energy released at various stages in the process is recovered and reused in the same process. The residual water is removed from the bioreactor.Type: ApplicationFiled: February 11, 2014Publication date: November 24, 2016Inventor: Artto Aurola
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Publication number: 20160240720Abstract: A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a MIG layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor. The device further includes a first conductivity type first contact, so that the pixel voltage is a potential difference between one of the pixel dopings and the first conductivity type first contact. The location of a main gate (983) corresponds at least partly to the location of a channel between the source and the drain. The device includes at least one extra gate (981, 982) horizontally displaced from the main gate (983).Type: ApplicationFiled: November 4, 2014Publication date: August 18, 2016Inventor: Artto AUROLA
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Patent number: 8426897Abstract: An improved semiconductor apparatus that comprises an elongated structure that extends into the substrate. The apparatus comprises a collection contact, a resistive path, a bias connection that creates along the length of the elongated structure, an electric field component that drives signal charge carriers in a direction perpendicular to the elongated structure, and a second bias that generates a current flow that creates within the substrate a constant electric field component to drive signal charge carriers towards the collection contact on the first surface.Type: GrantFiled: December 1, 2006Date of Patent: April 23, 2013Inventor: Artto Aurola
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Patent number: 8288837Abstract: A semiconductor radiation detector comprises a bulk layer of semiconductor material, and on a first surface of the bulk layer in the following order: a modified internal gate layer of semiconductor of second conductivity type, a barrier layer of semiconductor of first conductivity type and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create pixels corresponding to pixel dopings. The device comprises a first conductivity type first contact. Said pixel voltage is defined as a potential difference between the pixel doping and the first contact. The bulk layer is of the first conductivity type. On a second surface of the bulk layer opposite to the first surface, there is nonconductive back side layer that would transport secondary charges outside the active area of the device or function as the radiation entry window.Type: GrantFiled: February 17, 2006Date of Patent: October 16, 2012Inventor: Artto Aurola
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Patent number: 8148760Abstract: A semiconductor radiation detector device, comprising a bulk layer (103) of semiconductor material, and on the first surface of the bulk layer (303) in the following order: a modified internal gate layer (104) of semiconductor material of second conductivity type, a barrier layer (305) of semiconductor material of first conductivity type and pixel dopings (131, 132, 133) of semiconductor material of the second conductivity type, adapted to be coupled to at least one pixel voltage in order to create pixels corresponding to pixel dopings, characterized in that the device comprises a first contact of first conductivity type and said pixel voltage is defined as the potential difference between the pixel doping and the first contact.Type: GrantFiled: December 29, 2006Date of Patent: April 3, 2012Inventor: Artto Aurola
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Patent number: RE49704Abstract: A semiconductor radiation detector device includes a semiconductor substrate. On one surface of the substrate are a MIG layer (241) of semiconductor of second conductivity type, a barrier layer (251) of semiconductor of first conductivity type, and pixel dopings of semiconductor of the second conductivity type. The pixel dopings are adapted to be coupled to at least one pixel voltage in order to create a source and a drain of a pixel-specific transistor. The device further includes a first conductivity type first contact, so that the pixel voltage is a potential difference between one of the pixel dopings and the first conductivity type first contact. The location of a main gate (983) corresponds at least partly to the location of a channel between the source and the drain. The device includes at least one extra gate (981, 982) horizontally displaced from the main gate (983).Type: GrantFiled: September 16, 2020Date of Patent: October 17, 2023Inventor: Artto Aurola