Patents by Inventor Arun Kumar Varadarajan Rajagopal

Arun Kumar Varadarajan Rajagopal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7550995
    Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: June 23, 2009
    Assignee: Altera Corporation
    Inventors: Patrick Guilloteau, Rafael C. Camarota, Arun Kumar Varadarajan Rajagopal
  • Patent number: 7248070
    Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: July 24, 2007
    Assignee: Altera Corporation
    Inventors: Patrick Guilloteau, Rafael C. Camarota, Arun Kumar Varadarajan Rajagopal
  • Patent number: 6701427
    Abstract: A data processing apparatus for processing floating point instructions is responsive to a floating point instruction to apply a floating point operation to a number of operands to produce a final result, result data being generated during a predetermined pipelined stage with further processing then being performed on the result data in one or more subsequent pipelined stages to generate the final result. Exception determination logic determines whether an exception may occur during application of the floating point operation to the operands, and to prevent the execution unit applying the floating point operation to those operands if it is determined that an exception may occur. The exception determination logic is arranged to use at least some of the predetermined control data to compensate for differences between the forwarded result data and the final result relevant when determining whether an exception may occur when processing the second floating point instruction.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 2, 2004
    Assignee: ARM Limited
    Inventors: Christopher Neal Hinds, Arun Kumar Varadarajan Rajagopal