Abstract: A method and device for data conversion in a matrix compute apparatus. The apparatus includes an input buffer (IB) that receives one or more matrix inputs characterized by a first format and a compute device coupled to the IB device that is configured to determine a combined matrix output. The compute device determines a first matrix output using a first input portion of the matrix input and determines a second matrix output using a second input portion. The compute device then determines a combined matrix output in a second format using the first and second matrix outputs. Within the compute device, an alignment device can determine a rounded matrix output from the combined matrix output, and a partial products reduction (PPR) device can determine a reduced matrix output in a third format using the rounded matrix output, which is stored in an output buffer (OB) coupled to the compute device.

Abstract: A communication device includes an AFE configured to track and hold a first driving signal to produce a plurality of sample signals, a shift and hold module configured to store the plurality of sample signals, and an ADC configured to respectively convert the plurality of sample signals to a plurality of digitized sample signals, the ADC including a plurality of ADC slices. A DSP is configured to calibrate the AFE based on the plurality of ADC slices corresponding to the plurality of digitized sample signals and generate an output data stream comprising the plurality of digitized samples. A skew management module is configured to detect a skew of the plurality of digitized sample signals in the output data stream generated by the DSP module, generate a programmable skew offset based on the detected skew, and correct the skew in the output data stream based on the programmable skew offset.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

Abstract: Embodiments of the present invention include an apparatus that receives date from multiple lanes, which are then aligned and synchronized for transcoding and encoding.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Abstract: The present invention is directed to data communication systems and methods. More specifically, embodiments of the present invention provide techniques for transceivers to quickly identify FEC mode used in data communication. A transmitting transceiver embeds FEC mode information in a designated field of an alignment marker. The receiving transceiver acknowledges the receipt of the FEC mode information and processes the incoming data accordingly. There are other embodiments as well.