Abstract: A partial response QAM Modem is provided wherein a transmit signal is generated by modulating band limited, multilevel, partial response precoded data with inphase and quadrature carriers in inphase and quadrature phase channels, respectively, and summing the modulated outputs. The received signal is processed by a passband automatic complex equalizer. The equalized signal is delayed and then demodulated with recovered inphase and quadrature carriers to recover the inphase and quadrature phase baseband signals. The recovered baseband signals are sampled at appropriate instants to produce estimates of the transmitted symbols. These symbols are partial response decoded and processed by error correctors to improve the overall system performance. The error corrector outputs are decoded to convert the multilevel estimated data to binary data and the binary data of the two channels is summed to obtain estimates of the binary data transmitted.

Abstract: A system is provided for extracting the proper carrier phase from a single sideband suppressed carrier signal. A received signal is equalized and then product demodulated by estimated in-phase and quadrature carriers produced by a voltage controlled oscillator (VCO). The outputs of the in-phase and quadrature product demodulators are low-pass filtered producing corresponding in-phase and quadrature baseband signals. An estimator compares the in-phase baseband signal with reference levels, samples the output of the comparing circuit at the band rate and generates a sequence of estimated data signals. The error signal, which forms the input to the VCO, is produced by multiplying the recovered quadrature baseband signal with the estimated data signals and is proportional to the product of the square of the low pass filtered baseband signal and the sine of the difference between the phases of the received carrier and estimated carrier.

Abstract: A multi-level digital filter system applicable to modems is provided. The incoming data is read serially into M shift registers and read out in parallel by M further shift registers under the control of an M-bit clock, where M=log.sub.2 N and N is the number of levels. After appropriate conditioning by a logic control circuit, the parallel outputs are filtered separately by M digital shaping filters. The shaping filters each comprise a chain of shift registers the outputs of which are weighted by a resistor network and summed to produce a desired time response, which in an exemplary embodiment is the inverse Fourier transform of an ideal low-pass filter. Summing of the filter outputs produces an N-level signal. Specific examples of three-, four-, five-, six- and eight-level systems are disclosed.