Patents by Inventor Asad J. Mughal
Asad J. Mughal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11411137Abstract: A III-nitride optoelectronic device includes at least one n-type layer, an active region grown on or above the n-type layer, at least one p-type layer grown on or above the active region, and a tunnel junction grown on or above the p-type layer. A conductive oxide may be wafer bonded on or above the tunnel junction, wherein the conductive oxide comprises a transparent conductor and may contain light extraction features on its non-bonded face. The tunnel junction also enables monolithic incorporation of electrically-injected and optically-pumped III-nitride layers, wherein the optically-pumped III-nitride layers comprise high-indium-content III-nitride layers formed as quantum wells (QWs) that are grown on or above the tunnel junction. The optically-pumped high-indium-content III-nitride layers emit light at a longer wavelength than the electrically-injected III-nitride layers.Type: GrantFiled: February 6, 2017Date of Patent: August 9, 2022Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Asad J. Mughal, Stacy J. Kowsz, Robert M. Farrell, Benjamin P. Yonkee, Erin C. Young, Christopher D. Pynn, Tal Margalith, James S. Speck, Shuji Nakamura, Steven P. DenBaars
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Patent number: 10985285Abstract: A physical vapor deposition (e.g., sputter deposition) method for III-nitride tunnel junction devices uses metal-organic chemical vapor deposition (MOCVD) to grow one or more light-emitting or light-absorbing structures and electron cyclotron resonance (ECR) sputtering to grow one or more tunnel junctions. In another method, the surface of the p-type layer is treated before deposition of the tunnel junction on the p-type layer. In yet another method, the whole device (including tunnel junction) is grown using MOCVD and the p-type layers of the III-nitride material are reactivated by lateral diffusion of hydrogen through mesa sidewalls in the III-nitride material, with one or more lateral dimensions of the mesa that are less than or equal to about 200 ?m. A flip chip display device is also disclosed.Type: GrantFiled: August 17, 2017Date of Patent: April 20, 2021Assignee: The Regents of the University of CaliforniaInventors: Benjamin P. Yonkee, Asad J. Mughal, David Hwang, Erin C. Young, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Publication number: 20200335663Abstract: A III-nitride optoelectronic device includes at least one n-type layer, an active region grown on or above the n-type layer, at least one p-type layer grown on or above the active region, and a tunnel junction grown on or above the p-type layer. A conductive oxide may be wafer bonded on or above the tunnel junction, wherein the conductive oxide comprises a transparent conductor and may contain light extraction features on its non-bonded face. The tunnel junction also enables monolithic incorporation of electrically-injected and optically-pumped III-nitride layers, wherein the optically-pumped III-nitride layers comprise high-indium-content III-nitride layers formed as quantum wells (QWs) that are grown on or above the tunnel junction. The optically-pumped high-indium-content III-nitride layers emit light at a longer wavelength than the electrically-injected III-nitride layers.Type: ApplicationFiled: February 6, 2017Publication date: October 22, 2020Applicant: The Regents of the University of CaliforniaInventors: Asad J. Mughal, Stacy J. Kowsz, Robert M. Farrell, Benjamin P. Yonkee, Erin C. Young, Christopher D. Pynn, Tal Margalith, James S. Speck, Shuji Nakamura, Steven P. DenBaars
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Publication number: 20190207043Abstract: A physical vapor deposition (e.g., sputter deposition) method for III-nitride tunnel junction devices uses metal-organic chemical vapor deposition (MOCVD) to grow one or more light-emitting or light-absorbing structures and electron cyclotron resonance (ECR) sputtering to grow one or more tunnel junctions. In another method, the surface of the p-type layer is treated before deposition of the tunnel junction on the p-type layer. In yet another method, the whole device (including tunnel junction) is grown using MOCVD and the p-type layers of the III-nitride material are reactivated by lateral diffusion of hydrogen through mesa sidewalls in the III-nitride material, with one or more lateral dimensions of the mesa that are less than or equal to about 200 ?m. A flip chip display device is also disclosed.Type: ApplicationFiled: August 17, 2017Publication date: July 4, 2019Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Benjamin P. Yonkee, Asad J. Mughal, David Hwang, Erin C. Young, James S. Speck, Steven P. DenBaars, Shuji Nakamura
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Patent number: 10297721Abstract: A method for fabricating a Zinc Oxide (ZnO) conductive film on a semiconductor material, including depositing a doped ZnO seed layer on a diode, wherein the ZnO seed layer forms an electrical contact to the diode; and depositing a ZnO layer on the ZnO seed layer, wherein the ZnO seed layer and the ZnO layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising III-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the ZnO layers and the diode, and (2) a contact resistance, of a structure comprising the ZnO layers and the diode, is lower as compared to a contact resistance of a structure comprising the ZnO layer directly on the diode without the ZnO seed layer.Type: GrantFiled: February 28, 2018Date of Patent: May 21, 2019Assignee: The Regents of the University of CaliforniaInventors: Asad J. Mughal, Sang Ho Oh, Steven P. DenBaars
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Publication number: 20180190875Abstract: A method for fabricating a Zinc Oxide (ZnO) conductive film on a semiconductor material, including depositing a doped ZnO seed layer on a diode, wherein the ZnO seed layer forms an electrical contact to the diode; and depositing a ZnO layer on the ZnO seed layer, wherein the ZnO seed layer and the ZnO layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising III-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the ZnO layers and the diode, and (2) a contact resistance, of a structure comprising the ZnO layers and the diode, is lower as compared to a contact resistance of a structure comprising the ZnO layer directly on the diode without the ZnO seed layer.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Applicant: The Regents of the University of CaliforniaInventors: Asad J. Mughal, Sang Ho Oh, Steven P. DenBaars
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Patent number: 9935243Abstract: A method for fabricating a Zinc Oxide (ZnO) conductive film on a semiconductor material, including depositing a doped ZnO seed layer on a diode, wherein the ZnO seed layer forms an electrical contact to the diode; and depositing a ZnO layer on the ZnO seed layer, wherein the ZnO seed layer and the ZnO layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising III-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the ZnO layers and the diode, and (2) a contact resistance, of a structure comprising the ZnO layers and the diode, is lower as compared to a contact resistance of a structure comprising the ZnO layer directly on the diode without the ZnO seed layer.Type: GrantFiled: September 15, 2016Date of Patent: April 3, 2018Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Asad J. Mughal, Sang Ho Oh, Steven P. DenBaars
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Publication number: 20170077356Abstract: A method for fabricating a Zinc Oxide (ZnO) conductive film on a semiconductor material, including depositing a doped ZnO seed layer on a diode, wherein the ZnO seed layer forms an electrical contact to the diode; and depositing a ZnO layer on the ZnO seed layer, wherein the ZnO seed layer and the ZnO layer each have a thickness, a crystal quality, and a doping level such that (1) the diode comprising III-nitride material is turned on with a turn on voltage of 2.75 volts or less applied across the ZnO layers and the diode, and (2) a contact resistance, of a structure comprising the ZnO layers and the diode, is lower as compared to a contact resistance of a structure comprising the ZnO layer directly on the diode without the ZnO seed layer.Type: ApplicationFiled: September 15, 2016Publication date: March 16, 2017Applicant: The Regents of the University of CaliforniaInventors: Asad J. Mughal, Sang Ho Oh, Steven P. DenBaars