Patents by Inventor Asako Sekine

Asako Sekine has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Substrate bias switching unit for a low power processor
    Patent number: 8364988
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 29, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR
    Publication number: 20110208983
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Application
    Filed: May 5, 2011
    Publication date: August 25, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Yonetaro TOTSUKA, Koichiro ISHIBASHI, Hiroyuki MIZUNO, Osamu Nishii, Kunio UCHIYAMA, Takanori SHIMURA, Asako SEKINE, Yoichi KATSUKI, Susumu NARITA
  • Substrate bias switching unit for a low power processor
    Patent number: 7958379
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • SUBSTRATE BIAS SWITCHING UNIT FOR A LOW POWER PROCESSOR
    Publication number: 20100005324
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Application
    Filed: December 30, 2008
    Publication date: January 7, 2010
    Inventors: Yonetaro TOTSUKA, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Substrate bias switching unit for a low power processor
    Patent number: 7475261
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: January 6, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Low power processor
    Publication number: 20040158756
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Application
    Filed: February 2, 2004
    Publication date: August 12, 2004
    Applicant: Renesas Technology Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita
  • Processor for controlling substrate biases in accordance to the operation modes of the processor
    Patent number: 6715090
    Abstract: The feature of the present invention consists in: a processor main circuit for executing program instruction strings on a processor chip; a substrate bias switching unit for switching voltages of substrate biases applied to a substrate of the processor main circuit; and an operation mode control unit for controlling, in response to the execution of an instruction to proceed to a stand-by mode in the processor main circuit, the substrate bias switching unit in such a way that the biases are switched over to voltages for the stand-by mode, and for controlling, in response to an interruption of the stand-by release from the outside, the substrate bias switching unit in such a way that the biases are switched over to voltages for a normal mode, and also for releasing, after the bias voltages switched thereto have been stabilized, the stand-by of the processor main circuit to restart the operation.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: March 30, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Yonetaro Totsuka, Koichiro Ishibashi, Hiroyuki Mizuno, Osamu Nishii, Kunio Uchiyama, Takanori Shimura, Asako Sekine, Yoichi Katsuki, Susumu Narita