Abstract: A plurality of semiconductor portions are arranged in a first direction to be spaced apart from each other. A heterojunction of each of the plurality of semiconductor portions extends in a second direction perpendicular to a first direction aligned with a c-axis of a first nitride semiconductor portion. Each of a plurality of first electrodes overlaps with an associated one of the plurality of semiconductor portions in a third direction perpendicular to both of the first direction and the second direction, and is directly electrically connected to the heterojunction of the associated semiconductor portion. Each of the plurality of second electrodes is located, with respect to an associated one of the plurality of semiconductor portions, opposite in the third direction from one of the plurality of first electrodes that overlaps with the associated semiconductor portion, and is directly electrically connected to the heterojunction of the associated semiconductor portion.

Abstract: A semiconductor portion thereof includes a heterojunction defining a junction between a first compound semiconductor portion and a second compound semiconductor portion having a greater bandgap than the first compound semiconductor portion. The heterojunction intersects with a second direction defined along a first surface of a substrate. A first electrode is arranged opposite from the substrate with respect to the semiconductor portion. A second electrode is arranged on a second surface of the substrate. A gate electrode intersects with the second direction between the first electrode and the second electrode and faces the second compound semiconductor portion. A gate layer is interposed in the second direction between the gate electrode and the second compound semiconductor portion and forms a depletion layer in the second compound semiconductor portion and the first compound semiconductor portion.

Abstract: A semiconductor device includes a substrate, a semiconductor portion, a first electrode, and a second electrode. The substrate has a first surface and a second surface located opposite from each other in a thickness direction defined for the substrate. The semiconductor portion is provided on the first surface of the substrate. The semiconductor portion includes a heterojunction defining a junction between a first compound semiconductor portion and a second compound semiconductor portion and intersecting with a first direction defined along the first surface of the substrate. The first electrode and the second electrode are arranged on a first end surface of the semiconductor portion and on a second end surface of the semiconductor portion, respectively, in a second direction defined along the first surface of the substrate and aligned with a direction in which the heterojunction extends. The first electrode and the second electrode are electrically connected to the heterojunction.

Abstract: A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

Abstract: A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a source-side nitride semiconductor regrowth layer which is located on a source-side recess region; a drain-side nitride semiconductor regrowth layer which is located on a drain-side recess region located apart from the source-side recess region; a first diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the source-side nitride semiconductor regrowth layer; and a second diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the drain-side nitride semiconductor regrowth layer.

Abstract: A diamond multilayer structure comprises: a nitride semiconductor layer that have a first main surface and a second main surface and comprises a nitride semiconductor having a wurtzite structure and containing B; and a diamond layer located on the first main surface of the nitride semiconductor layer.

Abstract: A nitride semiconductor device according to one embodiment of the present disclosure includes: a substrate; a first nitride semiconductor layer supported by the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a source-side nitride semiconductor regrowth layer which is located on a source-side recess region; a drain-side nitride semiconductor regrowth layer which is located on a drain-side recess region located apart from the source-side recess region; a first diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the source-side nitride semiconductor regrowth layer; and a second diffusion layer which is disposed in the first nitride semiconductor layer and contains Ge diffused from the drain-side nitride semiconductor regrowth layer.

Abstract: A nitride semiconductor device of the present invention has a source-electrode-side insulator protection film layer disposed between a source electrode and a drain electrode on a second nitride semiconductor layer and formed at least partially covering the source electrode, a drain-electrode-side insulator protection film layer disposed separately from the source-electrode-side insulator protection film layer and formed at least partially covering the drain electrode, and a gate layer formed in contact with the second nitride semiconductor layer between the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and made of a p-type metal oxide semiconductor, and the gate layer has regions opposite to the second nitride semiconductor layer across each of the source-electrode-side insulator protection film layer and the drain-electrode-side insulator protection film layer and a region in contact with the second nitride semiconductor layer.

Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

Abstract: The present invention relates to a semiconductor device having a multi-layered structure comprising an emitter layer, a base layer, and a collector layer, each composed of a group III-V n-type compound semiconductor in this order; a quantum dot barrier layer disposed between the emitter layer and the base layer; a collector electrode, a base electrode and the emitter layer all connected to an emitter electrode; the quantum dot barrier layer having a plurality of quantum dots being sandwiched between first and second barrier layers from the emitter layer side and the base layer side, respectively and each having a portion that is convex to the base layer; a base layer side interface in the second barrier layer, and collector layer side and emitter layer side interfaces in the base layer having curvatures that are convex to the collector layer corresponding to the convex portions of the quantum dots.

Abstract: A ballistic semiconductor device of the present invention comprises a n-type emitter layer (102), a base layer (305) made of n-type InGaN, a n-type collector layer (307), an emitter barrier layer (103) interposed between the emitter layer (102) and the base layer (305) and having a band gap larger than that of the base layer (305), and a collector barrier layer (306) interposed between the base layer (305) and the collector layer (307) and having a band gap larger than that of the base layer (305), and operates at 10 GHz or higher.

Abstract: A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and

Abstract: A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple ?-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple ?-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple ?-doped InAlAs layer (204) as a carrier supplying layer is reduced.

Abstract: The present invention relates to a semiconductor device comprising a substrate (101); a semiconductor multi-layered structure formed on the substrate (101); the semiconductor multi-layered structure comprising an emitter layer (102), a base layer (105), and a collector layer (107), each composed of a group III-V n-type compound semiconductor and layered in this order; a quantum dot barrier layer (103) disposed between the emitter layer (102) and the base layer (105); a collector electrode (110), a base electrode (111) and an emitter electrode (112) connected to the collector layer (107), the base layer (105) and the emitter layer (102), respectively; the quantum dot barrier layer (103) comprising a plurality of quantum dots (103c); the quantum dots (103) being sandwiched between first and second barrier layers (103a, 103d) from the emitter layer side and the base layer side, respectively; each of the quantum dots (103c) having a convex portion that is convex to the base layer (105); a base layer (105) side in

Abstract: A hetero field effect transistor according to the present invention comprises an InP substrate, a channel layer provided on the InP substrate with a buffer layer disposed between the InP substrate and the channel layer, a spacer layer constituted by a semiconductor having a band gap larger than that of the channel layer formed to hetero-join to the channel layer, and a carrier supply layer formed to be adjacent to the spacer layer, wherein the channel layer comprises a predetermined semiconductor layer constituted by a compound semiconductor represented by a formula GaxIn1?xNyA1?y in which A is As or Sb, composition x satisfies 0?x?0.2, and composition y satisfies 0.03?y?0.10.

Abstract: A hetero field effect transistor according to the present invention comprises an InP substrate, a channel layer provided on the InP substrate with a buffer layer disposed between the InP substrate and the channel layer, a spacer layer constituted by a semiconductor having a band gap larger than that of the channel layer formed to hetero-join to the channel layer, and a carrier supply layer formed to be adjacent to the spacer layer, wherein the channel layer comprises a predetermined semiconductor layer constituted by a compound semiconductor represented by a formula GaxIn1−xNyA1−y in which A is As or Sb, composition x satisfies 0≦x≦0.2, and composition y satisfies 0.03≦y≦0.10.

Abstract: A plasma oscillation switching device of the present invention comprises semiconductor substrate 101; first barrier layer 103 that is composed of a III-V compound semiconductor and formed on the substrate; channel layer 104 that is composed of a III-V compound semiconductor and formed on the first barrier layer; second barrier layer 105 that is composed of a III-V compound semiconductor and formed on the channel layer; source electrode 107, gate electrode 109 and drain electrode 108 provided on the second barrier layer, wherein the first barrier layer includes n-type diffusion layer 103a, the second barrier layer includes p-type diffusion layer 105a, the band gap of the channel layer is smaller than the band gaps of the first and the second barrier layers, two-dimensional electron gas EG is accumulated at the conduction band at the boundary between the first barrier layer and the channel layer, two-dimensional hole gas HG is accumulated at the valence band at the boundary between the second barrier layer and

Abstract: A HEMT has an InAlAs layer (202), an InGaAs layer (203), a multiple &dgr;-doped InAlAs layer (204) composed of n-type doped layers (204a) and undoped layers (204b) which are alternately stacked, an InP layer (205), a Schottky gate electrode (210), a source electrode (209a), and a drain electrode (209b) on an InP substrate (201). When a current flows in a region (channel region) of the InGaAs layer (203) adjacent the interface between the InGaAs layer (203) and the multiple &dgr;-doped InAlAs layer (204), a breakdown voltage in the OFF state can be increased, while resistance to the movement of carriers passing through the multiple &dgr;-doped InAlAs layer (204) as a carrier supplying layer is reduced.

Abstract: An avalanche photodiode (APD) of the present invention uses a distortion-compensated superlattice multiplication layer (103) for the superlattice multiplication layer. It also uses a multi-layered light-reflecting layer as the light-reflecting layer. This structure of the present invention makes it possible to reduce a layer thickness of the superlattice multiplication layer without decreasing an electron multiplication factor and increasing a dark current. Accordingly, the APD of the present invention shows high response and low operating voltage, while it also maintains low dark current, low noise and broad band at the same time.

Abstract: An avalanche photodiode (APD) of the present invention uses a distortion-compensated superlattice multiplication layer (103) for the superlattice multiplication layer. It also uses a multi-layered light-reflecting layer as the light-reflecting layer. This structure of the present invention makes it possible to reduce a layer thickness of the superlattice multiplication layer without decreasing an electron multiplication factor and increasing a dark current. Accordingly, the APD of the present invention shows high response and low operating voltage, while it also maintains low dark current, low noise and broad band at the same time.