Patents by Inventor Ashay A. Dani

Ashay A. Dani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240222283
    Abstract: Methods and apparatus to prevent over-etch in semiconductor packages are disclosed. A disclosed example semiconductor package includes at least one dielectric layer, an interconnect extending at least partially through or from the at least one dielectric layer, and a material on at least a portion of the interconnect, wherein the material comprises at least one of silicon or titanium.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Hongxia Feng, Bohan Shan, Bai Nie, Xiaoxuan Sun, Holly Sawyer, Tarek Ibrahim, Adwait Telang, Dingying Xu, Leonel Arana, Xiaoying Guo, Ashay Dani, Sairam Agraharam, Haobo Chen, Srinivas Pietambaram, Gang Duan
  • Publication number: 20240222301
    Abstract: Methods and apparatus for optical thermal treatment in semiconductor packages are disclosed. A disclosed example integrated circuit (IC) package includes a dielectric substrate, an interconnect associated with the dielectric substrate, and light absorption material proximate or surrounding the interconnect, the light absorption material to increase in temperature in response to being exposed to a pulsed light for thermal treatment corresponding to the IC package.
    Type: Application
    Filed: December 28, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Hongxia Feng, Haobo Chen, Srinivas Pietambaram, Bai Nie, Gang Duan, Kyle Arrington, Ziyin Lin, Yiqun Bai, Xiaoying Guo, Dingying Xu, Sairam Agraharam, Ashay Dani, Eric J. M. Moret, Tarek Ibrahim
  • Publication number: 20240222136
    Abstract: Mechanical or chemical processes can form roughened surfaces which can be used for coupling layers of electrical systems such as when forming dies, substrates, computer chips or the like that, when subjected to high stress, are robust enough to remain coupled together.
    Type: Application
    Filed: December 29, 2022
    Publication date: July 4, 2024
    Inventors: Bohan Shan, Haobo Chen, Srinivas Venkata Ramanuja Pietambaram, Hongxia Feng, Gang Duan, Xiaoying Guo, Ashay A. Dani, Yiqun Bai, Dingying Xu, Bai Nie, Kyle Jordan Arrington, Wei Wei, Ziyin Lin
  • Publication number: 20240203853
    Abstract: An electronic device and associated methods are disclosed. In one example, the electronic device can include a substrate, a via, a build-up layer, a top layer, and one or more dies. The substrate can include a conductor coating. The via can be connected to the conductor coating. The build-up layer can be on the substrate. The build-up layer can define a channel that the via is formed within and insulate the via during operation of the electronic device. The top layer can be interproximal to the substrate and the via. The one or more dies can be connected to the via.
    Type: Application
    Filed: December 20, 2022
    Publication date: June 20, 2024
    Inventors: Bohan Shan, Haobo Chen, Hongxia Feng, Julianne Troiano, Dingying Xu, Matthew Tingey, Xiaoying Guo, Srinivas Venkata Ramanuja Pietambaram, Bai Nie, Gang Duan, Bin Mu, Kyle Mcelhinny, Ashay A. Dani, Leonel R. Arana
  • Publication number: 20230317653
    Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for hybrid bonding a die to a substrate. In embodiments, the die may be a chiplet that is bonded to an interconnect. In embodiments, the die may be a plurality of dies, where the plurality of dies are hybrid bonded to a substrate, to each other, or a combination of both. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 30, 2022
    Publication date: October 5, 2023
    Inventors: Hongxia FENG, Xiaoxuan SUN, Amey Anant APTE, Dingying David XU, Sairam AGRAHARAM, Gang DUAN, Ashay DANI
  • Patent number: 11335616
    Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. A semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Malavarayan Sankarasubramanian, Yongki Min, Ashay A. Dani, Kaladhar Radhakrishnan
  • Publication number: 20210098326
    Abstract: A semiconductor package may include a composite magnetic inductor that is formed integral with the semiconductor substrate. The composite magnetic inductor may include a composite magnetic resin layer and a plurality of conductive layers arranged such that the composite magnetic resin layer is interleaved between successive conductive layers. The resultant composite magnetic inductor may be disposed between dielectric layers. A core layer may be disposed proximate the composite magnetic inductor. A build-up layer may be disposed proximate the core layer or proximate the composite magnetic inductor in a coreless semiconductor substrate. semiconductor die may couple to the build-up layer. The composite magnetic inductor beneficially provides a greater inductance than external inductors coupled to the semiconductor package.
    Type: Application
    Filed: April 28, 2017
    Publication date: April 1, 2021
    Applicant: Intel Corporation
    Inventors: Malavarayan Sankarasubramanian, Yongki Min, Ashay A. Dani, Kaladhar Radhakrishnan
  • Publication number: 20200203067
    Abstract: The inductor includes a plurality of inductive elements that are at least partially encapsulated, covered, or embedded in a composite magnetic material that improves the inductance of the inductor without a corresponding, detrimental, increase in the size of the inductor. The composite magnetic material includes a plurality of magnetic particles dispersed in a carrier medium. Each of the magnetic particles includes a magnetic core that is encapsulated in a dielectric magnetic coating. The dielectric magnetic coating is a thermally stable material having high electrical resistivity.
    Type: Application
    Filed: September 29, 2017
    Publication date: June 25, 2020
    Applicant: Intel Corporation
    Inventors: Malavarayan Sankarasubramanian, Yongki Min, Ashay Dani
  • Patent number: 10049971
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Publication number: 20170207152
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: April 3, 2017
    Publication date: July 20, 2017
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9613933
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 4, 2017
    Assignee: Intel Corporation
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, Jr., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9247686
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: January 26, 2016
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Publication number: 20150255415
    Abstract: An apparatus is described that includes a substrate and a mold compound disposed on the substrate. The semiconductor die is embedded within the mold compound and is electrically coupled to lands on the substrate. Solder balls are disposed around the semiconductor die on the substrate. Each of the solder balls have a solid coating thereon. The solid coating contains a cleaning agent to promote its solder ball's coalescence with another solder ball. Respective vias are formed in the mold compound that expose the solder balls and their respective solid coatings. In combined or alternate embodiments outer edges of the mold compound have smaller thickness than regions of the mold compound between the vias and the semiconductor die. In combined or alternate embodiments micro-channels exist between the solder balls and the mold compound.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 10, 2015
    Inventors: Thomas J. De Bonis, Lilia May, Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Edward R. Prack, Carl L. Deppisch, Anna M. Prakash, James C. Matayabas, JR., Jason Jieping Zhang, Srinivasa R. Aravamudhan, Chang Lin
  • Patent number: 9024453
    Abstract: Interconnect packaging technology for direct-chip-attach, package-on-package, or first level and second level interconnect stack-ups with reduced Z-heights relative to ball technology. In embodiments, single or multi-layered interconnect structures are deposited in a manner that permits either or both of the electrical and mechanical properties of specific interconnects within a package to be tailored, for example based on function. Functional package interconnects may vary one of more of at least material layer composition, layer thickness, number of layers, or a number of materials to achieve a particular function, for example based on an application of the component(s) interconnected or an application of the assembly as a whole. In embodiments, parameters of the multi-layered laminated structures are varied dependent on the interconnect location within an area of a substrate, for example with structures having higher ductility at interconnect locations subject to higher stress.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: May 5, 2015
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Ashay A. Dani, Martha A. Dudek
  • Publication number: 20140182763
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Application
    Filed: March 5, 2014
    Publication date: July 3, 2014
    Inventors: Saikumar JAYARAMAN, Paul A. KONING, Ashay DANI
  • Publication number: 20140175160
    Abstract: A composition including a solder flux including a rosin material have a property to maintain a less than 10 percent drop in tackiness from an initial tackiness value of 20 gf to 120 gf over a temperature regime of 20° C. to 200° C. A composition including a solder powder; and a solder flux including a rosin material including a softening temperature of 150° C. to 200° C. and a molecular weight of 300 g/mol to 600 g/mol. A method including introducing a solder paste to one or more contact pads of a substrate, the solder paste including a solder powder and a solder flux including a rosin material including a softening temperature of 150° C. to 190° C. and a molecular weight of 300 g/mol to 600 g/mol; contacting the solder paste with a solder ball of a package substrate; and heating the solder paste.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Inventors: Rajen S. Sidhu, Mukul P. Renavikar, Ashay A. Dani, Martha A. Dudek
  • Patent number: 8701281
    Abstract: Surface-active dopants are added to a portion of a circuit package before a reflow process to promote wetting and reduce the formation of solder bump bridges. The circuit package has a solder element that electrically connects the circuit package to a substrate. A reflow process is performed to attach the solder element to a pad on the circuit package. During the reflow process, the surface-active dopants diffuse to the surface of the solder element and form an oxide passivation layer on the surface of the solder element.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Rajen S. Sidhu, Ashay A. Dani, Mukul P. Renavikar
  • Patent number: 8703286
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Grant
    Filed: April 20, 2011
    Date of Patent: April 22, 2014
    Assignee: Intel Corporation
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani
  • Patent number: 7996989
    Abstract: Embodiments of the invention includes a heat dissipating device. The heat dissipating device includes a main body having a surface, wherein the surface is plated or coated with at least two different metals to form a design effective for bonding to solder and for adhering to polymer in a polymer solder hybrid. The heat dissipating device also includes surface perturbations.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: August 16, 2011
    Assignee: Intel Corporation
    Inventors: Ashay A. Dani, Sabina J. Houle, Christopher L. Rumer, Thomas J Fitzgerald
  • Publication number: 20110194254
    Abstract: Embodiments of the present invention provide various polymeric matrices that may be used as a binder matrix for polymer solder hybrid thermal interface materials. In alternative embodiments the binder matrix material may be phophozene, perfluoro ether, polyether, or urethane. For one embodiment, the binder matrix is selected to provide improved adhesion to a variety of interfaces. For an alternative embodiment the binder matrix is selected to provide low contact resistance. In alternative embodiments, polymeric materials containing fusible and non-fusible particles may be used in application where heat removal is desired and is not restricted to thermal interface materials for microelectronic devices.
    Type: Application
    Filed: April 20, 2011
    Publication date: August 11, 2011
    Inventors: Saikumar Jayaraman, Paul A. Koning, Ashay Dani