Patents by Inventor Ashima B. Chakravarti
Ashima B. Chakravarti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8900961Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: October 19, 2010Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
-
Patent number: 8685845Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.Type: GrantFiled: August 20, 2010Date of Patent: April 1, 2014Assignee: International Business Machines CorporationInventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
-
Patent number: 8575655Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: GrantFiled: March 27, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
-
Patent number: 8563446Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: GrantFiled: May 18, 2012Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
-
Patent number: 8440547Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: GrantFiled: February 9, 2009Date of Patent: May 14, 2013Assignee: International Business Machines CorporationInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
-
Patent number: 8389352Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: GrantFiled: February 11, 2011Date of Patent: March 5, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
-
Patent number: 8354314Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: GrantFiled: February 11, 2011Date of Patent: January 15, 2013Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
-
Publication number: 20130009211Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: ApplicationFiled: September 14, 2012Publication date: January 10, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
-
Publication number: 20120228736Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: ApplicationFiled: May 18, 2012Publication date: September 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
-
Publication number: 20120205749Abstract: Epitaxial deposition of silicon germanium in a semiconductor device is achieved without using masks. Nucleation delays induced by interactions with dopants present before deposition of the silicon germanium are used to determine a period over which an exposed substrate surface may be subjected to epitaxial deposition to form a layer of SiGe on desired parts with substantially no deposition on other parts. Dopant concentration may be changed to achieve desired thicknesses within preferred deposition times. Resulting deposited SiGe is substantially devoid of growth edge effects.Type: ApplicationFiled: February 11, 2011Publication date: August 16, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashima B. Chakravarti, Abhishek Dube, Dominic J. Schepis
-
Patent number: 8236710Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: GrantFiled: October 7, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
-
Publication number: 20120181631Abstract: Various techniques for changing the workfunction of the substrate by using a SiGe channel which, in turn, changes the bandgap favorably for a p-type metal oxide semiconductor field effect transistors (pMOSFETs) are disclosed. In the various techniques, a SiGe film that includes a low doped SiGe region above a more highly doped SiGe region to allow the appropriate threshold voltage (Vt) for pMOSFET devices while preventing pitting, roughness and thinning of the SiGe film during subsequent cleans and processing is provided.Type: ApplicationFiled: March 27, 2012Publication date: July 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Stephen W. Bedell, Ashima B. Chakravarti, Michael P. Chudzik, Judson R. Holt, Dominic J. Schepis
-
Patent number: 8173524Abstract: Methods form epitaxial materials by forming at least two gate stacks on a silicon substrate and forming sidewall spacers on sides of the gate stacks. Such methods pattern a recess in the silicon substrate between adjacent ones of the gate stacks. The methods also provide a liner in a bottom of the recess, and epitaxially grow epitaxial material from sidewalls of the recess to fill the recess with the epitaxial material.Type: GrantFiled: January 11, 2011Date of Patent: May 8, 2012Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Abhishek Dube, Dominic J. Schepis
-
Publication number: 20120086103Abstract: A method for forming a trench structure is provided for a semiconductor and/or memory device, such as an DRAM device. In one embodiment, the method for forming a trench structure includes forming a trench in a semiconductor substrate, and exposing the sidewalls of the trench to an arsenic-containing gas to adsorb an arsenic containing layer on the sidewalls of the trench. A material layer is then deposited on the sidewalls of the trench to encapsulate the arsenic-containing layer between the material layer and sidewalls of the trench.Type: ApplicationFiled: October 7, 2010Publication date: April 12, 2012Applicant: International Business Machines CorporationInventors: ASHIMA B. CHAKRAVARTI, Jacob B. Dadson, Paul J. Higgins, Babar A. Khan, John J. Moore, Christopher C. Parks, Rohit S. Takalkar
-
Publication number: 20120043556Abstract: A method for depositing epitaxial films of silicon carbon (Si:C). In one embodiment, the method includes depositing an n-type doped silicon carbon (Si:C) semiconductor material on a semiconductor deposition surface using a deposition gas precursor composed of a silane containing gas precursor, a carbon containing gas precursor, and an n-type gas dopant source. The deposition gas precursor is introduced to the semiconductor deposition surface with a hydrogen (H2) carrier gas. The method for depositing epitaxial films may include an etch reaction provided by hydrogen chloride (HCl) gas etchant and a hydrogen (H2) carrier gas.Type: ApplicationFiled: August 20, 2010Publication date: February 23, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Abhishek Dube, Ashima B. Chakravarti, Jinghong H. Li, Rainer Loesing, Dominic J. Schepis
-
Patent number: 8105955Abstract: An integrated circuit system includes a substrate, a carbon-containing silicon region over the substrate, a non-carbon-containing silicon region over the substrate, and a silicon-carbon region, including the non-carbon-containing silicon region and the carbon-containing silicon region.Type: GrantFiled: August 15, 2006Date of Patent: January 31, 2012Assignees: GLOBALFOUNDRIES Singapore Pte. Ltd., International Business Machines CorporationInventors: Jin Ping Liu, Richard J. Murphy, Anita Madan, Ashima B. Chakravarti
-
Patent number: 8080451Abstract: Solutions for fabricating a semiconductor structure. One embodiment includes a method for fabricating a semiconductor structure, the method including: forming a first dielectric structure on a substrate, the first dielectric structure including silicon nitride (Si3N4); forming a second dielectric structure in proximity to the first dielectric structure; and growing a non-epitaxial thin film from a surface of the first dielectric structure; wherein the growing includes using a combination of precursor, carrier and etchant with a ratio among the precursor, carrier, and etchant being adjusted for selective growth of the thin film on the surface, and wherein the thin film includes one selected from a group consisting of: a monocrystalline material, an amorphous material, a polycrystalline material and a combination thereof.Type: GrantFiled: January 8, 2010Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Thomas N. Adam, Ashima B. Chakravarti, Eric C. T. Harley, Judson R. Holt
-
Patent number: 7888241Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: GrantFiled: June 9, 2008Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Nazle
-
Publication number: 20110034000Abstract: A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.Type: ApplicationFiled: October 19, 2010Publication date: February 10, 2011Applicant: International Business Machines CorporationInventors: Ashima B. Chakravarti, Anthony I. Chou, Toshiharu Furukawa, Steven J. Holmes, Wesley C. Natzle
-
Patent number: 7838932Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.Type: GrantFiled: February 8, 2008Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Dureseti Chidambarrao, Judson R. Holt, Yaocheng Liu, Kern Rim