Patents by Inventor Ashish Bijlani

Ashish Bijlani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11036479
    Abstract: A method including: parsing a program to identify a plurality of features within the program; performing a first match of the plurality of features to a plurality of code files based on a hierarchical code index, the features corresponding to leaf nodes of the hierarchical code index and the code files corresponding to parent nodes of the leaf nodes; normalizing the first match results to weight against common features; performing a second match of the plurality of code files to one or more code repositories based on the hierarchical code index; normalizing the second match results to weight against common files; and identifying a code repository of the one or more code repositories as being included within the program.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: June 15, 2021
    Assignee: Georgia Tech Research Corporation
    Inventors: Ruian Duan, Ashish Bijlani, Taesoo Kim, Wenke Lee
  • Publication number: 20200065074
    Abstract: A method including: parsing a program to identify a plurality of features within the program; performing a first match of the plurality of features to a plurality of code files based on a hierarchical code index, the features corresponding to leaf nodes of the hierarchical code index and the code files corresponding to parent nodes of the leaf nodes; normalizing the first match results to weight against common features; performing a second match of the plurality of code files to one or more code repositories based on the hierarchical code index; normalizing the second match results to weight against common files; and identifying a code repository of the one or more code repositories as being included within the program.
    Type: Application
    Filed: August 20, 2019
    Publication date: February 27, 2020
    Inventors: Ruian Duan, Ashish Bijlani, Taesoo Kim, Wenke Lee
  • Publication number: 20180232541
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.
    Type: Application
    Filed: April 9, 2018
    Publication date: August 16, 2018
    Applicant: INTEL CORPORATION
    Inventors: KOICHI YAMADA, PALANIVELRAJAN SHANMUGAVELAYUTHAM, LIOR MALKA, ASHISH BIJLANI
  • Patent number: 9940484
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: April 10, 2018
    Assignee: INTEL CORPORATION
    Inventors: Koichi Yamada, Palanivelrajan Shanmugavelayutham, Lior Malka, Ashish Bijlani
  • Patent number: 9665374
    Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 30, 2017
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Ashish Bijlani, Jiwei Lu, Cheng Yan Zhao
  • Publication number: 20160179547
    Abstract: A method is described. The method includes receiving an instruction, accessing a return cache to load a predicted return target address upon determining that the instruction is a return instruction, searching a lookup table for executable binary code upon determining that the predicted translated return target address is incorrect and executing the executable binary code to perform a binary translation.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Koichi Yamada, Ashish Bijlani, Jiwei Lu, Cheng Yan Zhao
  • Publication number: 20160180115
    Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: INTEL CORPORATION
    Inventors: KOICHI YAMADA, PALANIVELRAJAN SHANMUGAVELAYUTHAM, LIOR MALKA, ASHISH BIJLANI
  • Patent number: 8866826
    Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.
    Type: Grant
    Filed: February 10, 2011
    Date of Patent: October 21, 2014
    Assignee: Qualcomm Innovation Center, Inc.
    Inventors: Gregory A. Reid, Hanyu Cui, Praveen V. Arkeri, Ashish Bijlani
  • Publication number: 20120206463
    Abstract: Parallel graphics-processing methods and mobile computing apparatus with parallel graphics-processing capabilities are disclosed. One exemplary embodiment of a mobile computing apparatus includes physical memory, at least two distinct graphics-processing devices, and a bus coupled to the physical memory and the at least two graphics-processing devices. A virtual graphics processing component enables each of at least two graphics-processing operations to be executed, in parallel, by a corresponding one of the at least two distinct graphics-processing devices, which operate in the same memory surface at the same time.
    Type: Application
    Filed: February 10, 2011
    Publication date: August 16, 2012
    Applicant: QUALCOMM INNOVATION CENTER, INC.
    Inventors: Gregory A. Reid, Hanyu Cui, Praveen V. Arkeri, Ashish Bijlani