Patents by Inventor Ashwini Dwarakanath

Ashwini Dwarakanath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8909961
    Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: December 9, 2014
    Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.
    Inventors: Jeffrey Herman, Krishna Sitaraman, Jia An Huang, Stephen D. Presant, Ali Ibrahim, Ashwini Dwarakanath
  • Patent number: 8527794
    Abstract: An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: September 3, 2013
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ali Ibrahim, Ashwini Dwarakanath, Daniel Parrenas Shimizu
  • Publication number: 20130138977
    Abstract: Briefly, a method and apparatus adjusts the power consumption level of an integrated circuit by dynamically scaling the clock frequency based on the real-time determined power consumption level. In one example, the method and apparatus changes an actual clock frequency of the integrated circuit to an effective clock frequency based on the maximum clock frequency and the difference between the threshold power consumption level and the actual power consumption level of the integrated circuit in the previous sampling interval. In one example, an effective clock frequency of the integrated circuit in the current sampling interval is determined. In one example, the difference between the maximum and effective clock frequencies in the current sampling interval is proportional to the difference between the threshold and actual power consumption levels in the previous sampling interval. The actual clock frequency of the integrated circuit is changed to the determined effective clock frequency.
    Type: Application
    Filed: November 29, 2011
    Publication date: May 30, 2013
    Applicants: ADVANCED MICRO DEVICES, INC., ATI TECHNOLOGIES ULC
    Inventors: Jeffrey Herman, Krishna Sitaraman, Jia An Huang, Stephen D. Presant, Ali Ibrahim, Ashwini Dwarakanath
  • Publication number: 20110291746
    Abstract: An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 1, 2011
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ali Ibrahim, Ashwini Dwarakanath, Daniel Parrenas Shimizu