Patents by Inventor Asim A. Selcuk
Asim A. Selcuk has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7026691Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.Type: GrantFiled: April 25, 2001Date of Patent: April 11, 2006Assignee: Advanced Micro Devices, Inc.Inventors: Craig S. Sander, Rich K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6475868Abstract: Silicon-based, submicron-dimensioned MOS and/or CMOS transistor devices having substantially reduced source/drain junction-to-semiconductor substrate capacitance are formed by implanting oxygen atoms and/or molecules just below source/drain implant regions. Implantation conditions are selected to provide a peak oxygen implant concentration at a depth just below the ultimate source/drain junction depth. Subsequent thermal processing at elevated temperature results in source/drain dopant diffusion/activation and formation of a silicon oxide barrier layer or stratum just below the ultimate source/drain junction depth, thereby substantially reducing junction-to-substrate capacitance of refractory metal silicide-contact devices.Type: GrantFiled: August 17, 2000Date of Patent: November 5, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Ming Yin Hao, Asim Selcuk, Richard P. Rouse, Emi Ishida
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Patent number: 6383827Abstract: An electrical alignment test structure is provided that enables accurate in-process alignment measurements. Embodiments include forming two conductive layers whose alignment is be tested on the surface of a semiconductor substrate, one layer having a generally trapezoidal “shorting bar” with symmetrically stepped sides, and the other layer having a snake-like resistor “sladder” with two symmetrical sets of rung-like segments, whose ends correspond to the steps of the sides of the shorting bar. The ladder and the shorting bar are disposed with the shorting bar between the two sets of segments of the ladder, such that when the two layers are formed properly aligned, an equal number of segments of each set of segments of the ladder makes contact with the shorting bar. Thus, when the two layers are properly aligned, the resistance of each of the two sets of segments of the ladder is about the same. However, when the layers are out of alignment more than a predetermined amount (i.e.Type: GrantFiled: April 17, 2000Date of Patent: May 7, 2002Assignee: Advanced Micro Devices, Inc.Inventors: Todd Lukanc, Asim Selcuk
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Patent number: 6306738Abstract: A device and method to modulate a gate polysilicon doping profile by performing a sidewall implantation. The method includes forming a gate on a substrate and implanting ions through a sidewall in the gate. The ion implantation is performed by projecting the ions at an angle that is not perpendicular to the top surface of substrate and in a direction that is towards the surface of sidewall. The ion implantation process can be performed using a type of dopant that either increases or decreases the net dopant concentration in a gate polysilicon layer in a region of the gate adjacent the sidewall and adjacent a gate oxide layer.Type: GrantFiled: June 17, 1999Date of Patent: October 23, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Asim Selcuk
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Patent number: 6291864Abstract: A device and method for reducing parasitic capacitance between the gate and an adjacent conductive layer. A gate structure is provided having a polysilicon layer with recessed side portions. Sidewalls or spacers partially cover the sides of the polysilicon layer, while the exposed side portions of the polysilicon layer are etched to form the recessed side portions. The area that is etched away to form the recessed side portions accounts for the reduction in intra-level parasitic capacitance between the gate and adjacent conductive layers, such as local interconnect layers, interconnect layers, and contact layers. By removing the area etched away to form the recessed side portions, the separation between the gate and the conductive layer is increased, thereby inhibiting parasitic capacitance which, among other factors, is a function of the distance between two electrical components.Type: GrantFiled: May 12, 1999Date of Patent: September 18, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Asim Selcuk
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Patent number: 6287953Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET.Type: GrantFiled: February 29, 2000Date of Patent: September 11, 2001Assignee: Advanced Micro Devices, Inc.Inventors: Craig S. Sander, Rich K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christoper A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6200864Abstract: A method of asymmetrically doping a region beneath a gate by controlling the lateral surface profile of the gate using a mask. A first embodiment of the method includes forming a mask over the gate such that it extends beyond the opposing sides of the gate in an uneven manner. A second embodiment of the method includes forming a mask including sidewall spacers on both sides of the gate in an uneven manner. The uneven manner of providing the mask for ion implantation can be used to define an asymmetric lateral channel profile, which can be advantageously used to vary gate overlap, channel VT, or source/drain doping as necessary.Type: GrantFiled: June 23, 1999Date of Patent: March 13, 2001Assignee: Advanced Micro Devices, Inc.Inventor: Asim Selcuk
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Patent number: 6191034Abstract: A method of forming minimal gaps or spaces in conductive lines pattern for increasing the density of integrated circuits by first forming an opening in an insulating layer overlying the conductive line by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening, and using the sidewalls as a mask to remove, preferably by etching, a portion of the conductive line pattern substantially equal in size to the reduced opening.Type: GrantFiled: April 5, 1999Date of Patent: February 20, 2001Assignee: Advanced Micro DevicesInventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6165882Abstract: A device and method to reduce resistance in polysilicon gates by forming a highly conductive plug within a trench in the gate. This is achieved by etching a trench between nitride sidewalls and into the polysilicon layer and depositing a metal (e.g. tungsten) plug therein. Certain embodiments include a gate structure positioned on a silicon substrate and a gate oxide layer positioned on the silicon substrate, a polysilicon layer positioned on the gate oxide layer, a nitride layer, which includes nitride sidewalls, positioned on the polysilicon layer, and a tungsten plug that is positioned within a first trench portion between the nitride sidewalls and a second trench portion in the polysilicon layer.Type: GrantFiled: April 2, 1999Date of Patent: December 26, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Asim Selcuk
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Patent number: 6146954Abstract: A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal insulating space between polysilicon gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate of the FET. A portion of an insulating layer between the source and drain is removed prior to forming the gate. Preferably, an etch stop layer on the semiconductor substrate underlying the insulating layer is used in the method.Type: GrantFiled: July 21, 1998Date of Patent: November 14, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6130470Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath two polysilicon plates. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. The capacitive plates are deposited as a conformal layer polysilicon and then anisotropically etched to form plates on the side walls of the trench. A dielectric material such as silicon dioxide may be deposited between the polysilicon plates in the trench. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.Type: GrantFiled: March 24, 1997Date of Patent: October 10, 2000Assignee: Advanced Micro Devices, Inc.Inventor: Asim A. Selcuk
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Patent number: 6051881Abstract: A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect metallization can be misaligned and the selected gates will be protected by its etch barrier and not be exposed to the opening. Further, local interconnect conductive material can pass over a gate or unrelated resistor without shorting the gate/resistor.Type: GrantFiled: December 5, 1997Date of Patent: April 18, 2000Assignee: Advanced Micro DevicesInventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 6046088Abstract: A method of forming field isolation in a semiconductor substrate, such as shallow oxide trenches, for isolation of FET transistors, including complementary FETs such as CMOS, with selected sections of said trenches extending above the substrate and being coplanar with the upper surface of subsequently formed polysilicon gates. An etch protective layer is used during the formation and the filling of the trench openings so that the top of the trenches are coplanar with upper surface of the etch protective layer. Selected sections of the trenches are masked and protected prior to planarization of the non-masked trenches to the bottom edge of the etch protective layer. After deposition and planarization of the poly, the upper surface of a deposited polysilicon layer for forming polysilicon gates of FET transistors is coplanar and self-aligned with the upwardly extending selected sections of the field isolation trenches.Type: GrantFiled: December 5, 1997Date of Patent: April 4, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Craig S. Sander, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 5981995Abstract: A static random access memory (SRAM) cell has a decreased cell size and utilizes transistors disposed in a number of trenches. Four trenches generally contain six transistors associated with the memory cell. The transistors are provided as sidewall transistors which are coupled to buried bit lines, VSS nodes, and VDD nodes at the bottom of the trenches. A first trench includes a driver transistor and a load transistor which have gates coupled together by a bridge over the trench. Another bridge is provided over the bridge over the trench to couple the source of the load transistor to the drain of the driver transistor. The drain of the driver transistor is coupled to another drain of the access gate transistor. The access gate transistor is located in a trench with a access gate transistor from another cell. The buried bit line is located in the trench with the access gate transistors.Type: GrantFiled: June 13, 1997Date of Patent: November 9, 1999Assignee: Advanced Micro Devices, Inc.Inventor: Asim A. Selcuk
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Patent number: 5930659Abstract: A method of forming minimal gaps or spaces in a polysilicon conductive lines pattern for increasing the density of integrated circuits by converting an area of the size of the desired gap or space in the polysilicon to silicon oxide, followed by removing the silicon oxide. The preferred method is to selectively ion implant oxygen into the polysilicon and annealing to convert the oxygen implanted polysilicon to silicon oxide. As an alternative method, an opening in an insulating layer overlying the conductive line is first formed by conventional optical lithography, followed by forming sidewalls in the opening to create a reduced opening and using the sidewalls as a mask to blanket implant oxygen through the reduced opening and into the exposed polysilicon conductive line. After annealing, the implanted polysilicon converted to silicon oxide and removed to form a gap or space in the polysilicon conductive line pattern substantially equal in size to the reduced opening.Type: GrantFiled: December 5, 1997Date of Patent: July 27, 1999Assignee: Advanced MicroDevices, Inc.Inventors: Richard K. Klein, Asim A. Selcuk, Nicholas J. Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst, Stephen C. Horne
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Patent number: 5889697Abstract: A memory cell for storing data having at least three logic states includes a pair of storage devices and third-level storage and refresh circuitry coupled to a pair of storage nodes. The storage devices maintain multi-level signals representative of first and second logic states at the pair of storage nodes. To store a third logic state, the third-level storage and refresh circuitry maintain the multi-level signals at both storage nodes at substantially equal intermediate levels.Type: GrantFiled: October 8, 1997Date of Patent: March 30, 1999Assignee: Advanced Micro DevicesInventors: Asim A. Selcuk, Craig S. Sander
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Patent number: 5879980Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath a polysilicon or tungsten plug. The polysilicon plugs are each isolated from the drains of lateral transistors associated with the SRAM cell. The capacitive structure is provided between first and second N-channel pull down transistors associated with the SRAM cell. The polysilicon plug can be provided during the formation of local interconnects for the cell. The polysilicon material or plug can be coupled to the semiconductor substrate.Type: GrantFiled: March 24, 1997Date of Patent: March 9, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Asim A. Selcuk, Raymond T. Lee
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Patent number: 5844836Abstract: A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected to drains of lateral transistors associated with the SRAM cell. A dielectric material such as silicon dioxide may be deposited between the local interconnect and polysilicon conductive lines. The capacitor structures are provided between first and second N-channel pull down transistors associated with the SRAM cell.Type: GrantFiled: March 24, 1997Date of Patent: December 1, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Nicholas John Kepler, Asim A. Selcuk, Richard K. Klein, Craig S. Sander, John C. Holst, Christopher A. Spence, Raymond T. Lee, Stephen C. Horne
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Patent number: 5796651Abstract: A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A drive circuit generates a reduced word line voltage to activate the pass transistor during a READ operation. The reduced word line voltage has a magnitude less than the magnitude of the bias voltage used to activate the pull-down transistor.Type: GrantFiled: May 19, 1997Date of Patent: August 18, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Stephen C. Horne, Richard K. Klein, Asim A. Selcuk, Nicholas John Kepler, Christopher A. Spence, Raymond T. Lee, John C. Holst
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Patent number: 5793671Abstract: An SRAM cell for use in a microprocessor includes enhancement mode load transistors. A control or bias circuit is coupled to the gates and drains of the load transistors to appropriately bias the load transistors. The bias circuit responds to feedback from a dummy cell to appropriately bias the load transistors. The bias circuit can operate in a refresh mode, a feedback mode, a bias mode, or access mode. The bias circuit allows the SRAM cell to operate quickly, stably, and with minimal current.Type: GrantFiled: January 21, 1997Date of Patent: August 11, 1998Assignee: Advanced Micro Devices, Inc.Inventor: Asim A. Selcuk