Patents by Inventor Aswani Aditya Kumar Tadinada

Aswani Aditya Kumar Tadinada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10686442
    Abstract: A method and apparatus for dynamically matching a plurality of resistors to a sensor are disclosed. In the method and apparatus, a switching block of a plurality of switching blocks receives a plurality of selection signals. The switching block is coupled to a resistor array having a plurality of resistors that are coupled in series and arranged in a closed loop. Each two resistors are coupled to each other by a respective resistor node of a plurality of resistor nodes. The switching block of the plurality of switching blocks has a plurality of input nodes and an output node, where the output node is coupled to the respective resistor node of the plurality of resistor nodes. In the method and apparatus, the switching block couples an input node of the plurality of input nodes to the output node based on the selection signals.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: June 16, 2020
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tanmoy Sen, Aswani Aditya Kumar Tadinada
  • Publication number: 20200089264
    Abstract: An electronic system having a linear voltage regulator and method of operating the linear voltage regulator. A linear voltage regulator of an electronic system has at least three ballast devices. The method of operating includes producing a voltage at an output terminal that is electrically coupled to a node of a first one of the three or more ballast devices; receiving a power mode indication; activating a first additional ballast device of the linear voltage regulator to add first additional capacitance to a load corresponding to the power mode; generating one or more successively delayed ballast control signals based at least in part on the power mode indication; and activating, using the successively delayed ballast control signals, second additional ballast devices of the linear voltage regulator to add second capacitances to the load of the linear voltage regulator.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 19, 2020
    Inventors: Kishan Reddy Gonapati, Aswani Aditya Kumar Tadinada, Manoja Dangeti
  • Patent number: 10579083
    Abstract: An electronic system having a linear voltage regulator and method of operating the linear voltage regulator. A linear voltage regulator of an electronic system has at least three ballast devices. The method of operating includes producing a voltage at an output terminal that is electrically coupled to a node of a first one of the three or more ballast devices; receiving a power mode indication; activating a first additional ballast device of the linear voltage regulator to add first additional capacitance to a load corresponding to the power mode; generating one or more successively delayed ballast control signals based at least in part on the power mode indication; and activating, using the successively delayed ballast control signals, second additional ballast devices of the linear voltage regulator to add second capacitances to the load of the linear voltage regulator.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: March 3, 2020
    Assignee: SYNAPTICS INCORPORATED
    Inventors: Kishan Reddy Gonapati, Aswani Aditya Kumar Tadinada, Manoja Dangeti
  • Publication number: 20200064875
    Abstract: A linear voltage regulator including a pass element, an error amplifier, and in-rush current protection (ICP) circuitry. The pass element is configured to produce an output voltage across a capacitor based on a received input voltage. The error amplifier is configured to output a control voltage based at least in part on the output voltage and a reference voltage. The control voltage is used to control a flow of output current through the pass element. The ICP circuitry is coupled to the pass element and the error amplifier and configured to maintain the output current below a threshold level while charging the capacitor from a discharged state to the output voltage.
    Type: Application
    Filed: October 5, 2018
    Publication date: February 27, 2020
    Inventors: Kishan Reddy Gonapati, Aswani Aditya Kumar Tadinada, Manoja Dangeti, Sivankumar Pandian
  • Publication number: 20180054197
    Abstract: A method and apparatus for dynamically matching a plurality of resistors to a sensor are disclosed. In the method and apparatus, a switching block of a plurality of switching blocks receives a plurality of selection signals. The switching block is coupled to a resistor array having a plurality of resistors that are coupled in series and arranged in a closed loop. Each two resistors are coupled to each other by a respective resistor node of a plurality of resistor nodes. The switching block of the plurality of switching blocks has a plurality of input nodes and an output node, where the output node is coupled to the respective resistor node of the plurality of resistor nodes. In the method and apparatus, the switching block couples an input node of the plurality of input nodes to the output node based on the selection signals.
    Type: Application
    Filed: October 13, 2017
    Publication date: February 22, 2018
    Inventors: Tanmoy Sen, Aswani Aditya Kumar Tadinada
  • Patent number: 9819344
    Abstract: An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: November 14, 2017
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Tanmoy Sen, Aswani Aditya Kumar Tadinada
  • Patent number: 9098097
    Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: August 4, 2015
    Assignee: STMicroelectronics International N.V.
    Inventors: Aswani Aditya Kumar Tadinada, Tanmoy Sen
  • Publication number: 20150130531
    Abstract: An integrated circuit die includes multiple temperature sensor units each for measuring the temperature of respective regions of a semiconductor substrate of the integrated circuit die. The temperature sensor units are each coupled to a multiplexer by respective groups of signal lines. The signal lines include resistance compensation areas for maintaining a particular ratio of resistances of the signal lines of each group.
    Type: Application
    Filed: November 13, 2013
    Publication date: May 14, 2015
    Applicant: STMicroelectronics International N.V.
    Inventors: Aswani Aditya Kumar TADINADA, Tanmoy SEN
  • Publication number: 20150061407
    Abstract: An apparatus comprising: a sensor; and a resistor array comprising a set of resistors; wherein on a first cycle: at least one first of said resistors is configured to provide a first resistance value; and on a second cycle: at least one second of said resistors is configured to provide said first resistance value.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Tanmoy Sen, Aswani Aditya Kumar Tadinada