Patents by Inventor Atsuhiro Sato
Atsuhiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180108418Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: October 23, 2017Publication date: April 19, 2018Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 9893078Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: GrantFiled: February 24, 2015Date of Patent: February 13, 2018Assignee: Toshiba Memory CorporationInventors: Toshifumi Minami, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara, Hideyuki Kamata, Teppei Higashitsuji
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Patent number: 9799403Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: June 6, 2016Date of Patent: October 24, 2017Assignee: Toshiba Memory CorporationInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9768189Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: April 7, 2016Date of Patent: September 19, 2017Assignee: TOSHIBA MEMORY CORPORATIONInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160358659Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: June 6, 2016Publication date: December 8, 2016Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Patent number: 9437300Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: GrantFiled: August 26, 2014Date of Patent: September 6, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Hideyuki Kamata, Toshifumi Minami, Teppei Higashitsuji, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Hiroshi Shinohara
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Publication number: 20160218109Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: April 7, 2016Publication date: July 28, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Patent number: 9361988Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: GrantFiled: August 26, 2014Date of Patent: June 7, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Masanobu Shirakawa, Takuya Futatsuyama, Kenichi Abe, Hiroshi Nakamura, Keisuke Yonehama, Atsuhiro Sato, Hiroshi Shinohara, Yasuyuki Baba, Toshifumi Minami
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Patent number: 9337145Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: GrantFiled: March 10, 2015Date of Patent: May 10, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi Shinohara, Atsuhiro Sato, Keisuke Yonehama, Yasuyuki Baba, Toshifumi Minami, Hiroyuki Maeda, Shinji Saito, Hideyuki Kamata
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Publication number: 20160071870Abstract: A semiconductor memory device includes a conducting layer and an insulating layer that are disposed above a semiconductor substrate, a plurality of pillars that extend in a direction which crosses a surface of the semiconductor substrate, and a plate that is disposed between the plurality of pillars and extends in the same direction as the pillars. A surface of the plate, which faces the pillars, has convex portions and non-convex portions.Type: ApplicationFiled: February 24, 2015Publication date: March 10, 2016Inventors: Toshifumi MINAMI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA, Hideyuki KAMATA, Teppei HIGASHITSUJI
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Publication number: 20160071793Abstract: According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.Type: ApplicationFiled: March 10, 2015Publication date: March 10, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Hiroshi SHINOHARA, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Toshifumi MINAMI, Hiroyuki MAEDA, Shinji SAITO, Hideyuki KAMATA
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Publication number: 20150262685Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Masanobu SHIRAKAWA, Takuya FUTATSUYAMA, Kenichi ABE, Hiroshi NAKAMURA, Keisuke YONEHAMA, Atsuhiro SATO, Hiroshi SHINOHARA, Yasuyuki BABA, Toshifumi MINAMI
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Publication number: 20150262669Abstract: A semiconductor memory device includes first and second memory cell transistors, first and second word lines electrically connected to the first and second memory cell transistors, respectively, first and second transfer transistors. The first and second transistors are electrically connected to the first and second word lines, respectively. The sizes of the first transistor and the second transistor are different.Type: ApplicationFiled: August 26, 2014Publication date: September 17, 2015Inventors: Hideyuki KAMATA, Toshifumi MINAMI, Teppei HIGASHITSUJI, Atsuhiro SATO, Keisuke YONEHAMA, Yasuyuki BABA, Hiroshi SHINOHARA
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Publication number: 20150062843Abstract: According to one embodiment, a semiconductor device includes a cell portion and a peripheral portion, including: a substrate, a first insulating layer disposed on the substrate, a first conductive layer disposed on the first insulating layer, a second insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the second insulating layer.Type: ApplicationFiled: March 12, 2014Publication date: March 5, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Teppei HIGASHITSUJI, Toshifumi MINAMI, Hideyuki KAMATA, Atsuhiro SATO, Keisuke YONEHAMA
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Patent number: 8581325Abstract: This semiconductor memory device comprises a semiconductor substrate, a plurality of tunnel insulator films formed on the substrate along a first direction and a second direction orthogonal to the first direction, a plurality of charge accumulation layers formed on the tunnel insulator films, respectively, a plurality of element isolation regions formed on the substrate, the element isolation regions including a plurality of trenches formed along the first direction between the tunnel insulator films, a plurality of element isolation films filled in the trenches, a plurality of inter-poly insulator films formed over the element isolation regions and on the upper and side surfaces of the charge accumulation layers along the second direction in a stripe shape, a plurality of air gaps formed between the element isolation films filled in the trenches and the inter-poly insulator films and a plurality of control gate electrodes formed on the inter-poly insulator films.Type: GrantFiled: March 6, 2012Date of Patent: November 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Fumitaka Arai
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Patent number: 8541829Abstract: A nonvolatile semiconductor memory includes a memory cell transistor including a first floating gate electrode layer formed on a first tunneling insulating film, a first inter-gate insulating film, first and second control gate electrode layers, and a first metallic silicide film; a high voltage transistor including a high voltage gate electrode layer formed on a high voltage gate insulating film, a second inter-gate insulating film having an aperture, third and fourth control gate electrode layers, and a second metallic silicide film; a low voltage transistor including a second floating gate electrode layer formed on a second tunneling insulating film, a third inter-gate insulating film having an aperture, fifth and sixth control gate electrode layers, and a third metallic silicide film; and a liner insulating film directly disposed on source and drain regions of each of the memory cell transistor, the low voltage transistor, and the high voltage transistor.Type: GrantFiled: September 19, 2011Date of Patent: September 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Kikuko Sugimae, Masayuki Ichige, Fumitaka Arai, Yasuhiko Matsunaga, Atsuhiro Sato
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Patent number: 8377814Abstract: A semiconductor memory device includes a first block having first memory cells and first select transistors, a second block having second memory cells and second select transistors, and arranged adjacent to the first block in a first direction, the second select transistor being arranged to face the first select transistor and commonly having a diffusion region with the first select transistor, a first interconnection layer provided on the diffusion region between the first and second blocks and extending in a second direction, and a second interconnection layer having a first portion provided in contact with an upper portion of the first interconnection layer and extending to a portion outside the first interconnection layer, and a second portion extending in the second direction and connected to the first portion in a portion outside a portion on the first interconnection layer.Type: GrantFiled: June 21, 2011Date of Patent: February 19, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Hiroyuki Nitta, Fumitaka Arai
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Patent number: 8330206Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.Type: GrantFiled: February 14, 2012Date of Patent: December 11, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
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Patent number: 8314455Abstract: A non-volatile semiconductor storage device includes: a memory cell area in which a plurality of electrically rewritable memory cells are formed; and a peripheral circuit area in which transistors that configure peripheral circuits to control the memory cells are formed. The memory cell area has formed therein: a semiconductor layer formed to extend in a vertical direction to a semiconductor substrate; a plurality of conductive layers extending in a parallel direction to, and laminated in a vertical direction to the semiconductor substrate; and a property-varying layer formed between the semiconductor layer and the conductive layers and having properties varying depending on a voltage applied to the conductive layers. The peripheral circuit area has formed therein a plurality of dummy wiring layers that are formed on the same plane as each of the plurality of conductive layers and that are electrically separated from the conductive layers.Type: GrantFiled: June 9, 2011Date of Patent: November 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi, Fumitaka Arai
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Patent number: 8270220Abstract: A nonvolatile semiconductor storage device includes a memory cell array and a peripheral circuit. The memory cell array includes active areas extending in a first direction, a dummy active area extending in the first direction, memory cells on the plurality of active areas, first dummy cells on the dummy active area, diffusion layer areas each connected to the corresponding memory cell and the corresponding first dummy cell, first contacts in the respective active areas, and a second contact in the dummy active area. The peripheral circuit includes a voltage applying unit configured to apply to each of the first contacts a first voltage to set each of the memory cells in a write enable state or a second voltage to set the memory cells in a write inhibit state, and to apply to the second contact a third voltage to change a threshold of the dummy cell.Type: GrantFiled: March 23, 2010Date of Patent: September 18, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Yasuhiro Shiino, Atsuhiro Sato, Takeshi Kamigaichi