Patents by Inventor Atsuhiro Suzuki

Atsuhiro Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10644018
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 5, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei Lee, Cheng-Hsien Cheng, Shaw-Hung Ku, Atsuhiro Suzuki
  • Publication number: 20190319033
    Abstract: A 3D NAND memory on a single integrated circuit is described including a block of vertical NAND strings, including a plurality of sub-blocks. Sub-blocks in the plurality of sub-blocks each comprise an upper select line in an upper level; word lines in intermediate levels below the upper level; a first lower select line in a first lower level below the intermediate levels; a second lower select line in a second lower level below the first lower level. A reference conductor can be disposed below the block. Bit lines are disposed over the block. Control circuitry applies voltages to the upper select lines, to the word lines and to the first and second lower select lines in the plurality of sub-blocks in various combinations for memory operations.
    Type: Application
    Filed: April 12, 2018
    Publication date: October 17, 2019
    Applicant: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Chih-Wei LEE, Cheng-Hsien CHENG, Shaw-Hung KU, Atsuhiro SUZUKI
  • Patent number: 10397139
    Abstract: According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 27, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kosuke Tatsumura, Atsuhiro Kinoshita, Hirotaka Nishino, Masamichi Suzuki, Yoshifumi Nishi, Takao Marukame, Takahiro Kurita
  • Patent number: 10340017
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: July 2, 2019
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Yu-Hung Huang, Cheng-Hsien Cheng, Chih-Wei Lee, Atsuhiro Suzuki, Wen-Jer Tsai
  • Publication number: 20190139615
    Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.
    Type: Application
    Filed: November 6, 2017
    Publication date: May 9, 2019
    Inventors: Shaw-Hung KU, Yu-Hung HUANG, Cheng-Hsien CHENG, Chih-Wei LEE, Atsuhiro SUZUKI, Wen-Jer TSAI
  • Patent number: 10262748
    Abstract: A non-volatile memory and a program method thereof are provided. The program method of the non-volatile memory includes: setting a first incremental value, and providing a plurality of first pulses of incrementally increasing voltages in sequence according to the first incremental value for performing a programming operation on a plurality of non-volatile memory cells during a first time period; and setting a second incremental value, and providing a plurality of second pulses of incrementally increasing voltages in sequence according to the second incremental value for performing a programming operation on the non-volatile memory cells during a second time period which is after the first time period, wherein the first incremental value is smaller than the second incremental value.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: April 16, 2019
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Ya-Jui Lee, Atsuhiro Suzuki
  • Publication number: 20190089723
    Abstract: Systems and methods are provided for generating samples of network traffic and characterizing the samples to easily identify exploits. A first embodiment of the present disclosure can generate traffic between a sample generator and the target computing device based on a particular exploit. The traffic can be a plurality of samples of the exploit using an exploit script. The method can provide for collecting and storing the plurality of samples. These samples can then be used to characterize the exploit by identifying invariant portions and variable portions of the samples. The method can further provide for removing any artifacts from the samples. Regular expressions can be constructed based on the samples. Each regular expression can be tested and ranked according to metrics of efficiency and accuracy.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 21, 2019
    Inventors: Victor C. VALGENTI, Ya-Wen LIN, Atsuhiro SUZUKI, Min Sik KIM
  • Patent number: 9859007
    Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: January 2, 2018
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
  • Publication number: 20170025179
    Abstract: Methods and apparatuses are contemplated herein for reducing bit-line recovery time of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of non-volatile memory cells, including a plurality of blocks, each block comprising a plurality of NAND strings, each of the NAND strings coupled to a bit line and word lines, the word lines arranged orthogonally to the NAND strings and establishing the memory cells at cross-points between surfaces of the NAND strings and the word lines, and a first set of discharge transistors positioned at an edge of the 3D array, coupled to a corresponding bit line, and configured for BL discharge, and a second set of discharge transistors positioned such that a first portion of BL potential is discharged through the first set of discharge transistors and a second portion through the second set.
    Type: Application
    Filed: July 24, 2015
    Publication date: January 26, 2017
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
  • Publication number: 20160372202
    Abstract: Methods and apparatuses are contemplated herein for enhancing the program performance of nonvolatile memory devices. In an example embodiment, a nonvolatile memory device comprises a 3D array of nonvolatile memory cells including a plurality of layers, each layer comprising NAND strings of nonvolatile memory cells, the NAND strings coupled to a bit line, and a plurality SSLs and word lines, the SSLs and the word lines arranged orthogonally to the NAND strings, the word lines establishing the nonvolatile memory cells at cross-points between surfaces of the plurality of NAND strings and the word lines, each of the NAND strings further comprising a plurality of SSL transistors coupling the SSLs to the NAND strings, wherein at least a first SSL being configured to receive a first voltage and a second SSL configured to receive at second voltage, and wherein the second SSL being nearer to the word lines.
    Type: Application
    Filed: June 17, 2015
    Publication date: December 22, 2016
    Inventors: Atsuhiro Suzuki, Chih-Wei Lee, Shaw-Hung Ku
  • Patent number: 9437319
    Abstract: Provided are methods, devices, and/or the like for reducing the bit line interference when programming non-volatile memory. One method comprises providing a non-volatile memory device comprising a set of cells, each cell associated with a bit line; shooting a programming voltage across each cell; detecting a threshold voltage for each cell; identifying a fast subset of the set of cells and a slow subset of the set of cells based at least in part on the detected threshold voltage for each cell; and shooting the programming voltage until the threshold voltage for each cell is greater than a verify voltage. For each shot a fast bit line bias is applied to the bit line associated each cell of the fast subset and a slow bit line bias is applied to the bit line associated with each cell of the slow subset.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 6, 2016
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Atsuhiro Suzuki, Ya Jui Lee, Kuan Fu Chen, Chih-Wei Lee
  • Patent number: 9318207
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: April 19, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kota Nishikawa, Masanori Hatakeyama, Takanori Eto, Atsuhiro Suzuki
  • Publication number: 20160049199
    Abstract: A nonvolatile semiconductor memory device according to an embodiment comprises a control unit, during a data erase, applying at least to a word line connected to a memory cell disposed most to a source line side a lower control voltage than that applied to a word line connected to a memory cell disposed most to a bit line side, of a plurality of word lines connected to at least a plurality of memory cells mutually written with data of an identical number of bits in a cell string.
    Type: Application
    Filed: December 15, 2014
    Publication date: February 18, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kota NISHIKAWA, Masanori Hatakeyama, Takanori Eto, Atsuhiro Suzuki
  • Patent number: 8991296
    Abstract: The compressor is provided with an oil separator for separating oil from refrigerant gas introduced into a separation chamber, an annular space for reserving oil separated from the refrigerant gas, and a reservoir chamber for reserving the thus separated oil. The oil separator is provided in a cylindrical hole formed in a discharge chamber from which the refrigerant gas is discharged and a lid for partitioning the cylindrical hole from the discharge chamber is provided in the cylindrical hole. The oil separator introduces the refrigerant gas from the discharge chamber to the separation chamber via the introduction passage. The annular space is provided around the lid and connected to the reservoir chamber via an oil passage. The reservoir chamber is connected to a crank chamber of a pressure lower than that in the discharge chamber.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Yoshinori Inoue, Hirokazu Mesaki, Masaya Sakamoto, Atsuhiro Suzuki, Akinobu Kanai, Tomoji Tarutani, Naoki Koeda, Osamu Nakayama
  • Patent number: 8390076
    Abstract: According to an aspect of the present invention, there is provided a semiconductor device including: a semiconductor substrate; active areas with island-like shapes formed on the semiconductor substrate; an element isolation area surrounding the active areas and including an element isolation groove formed on the semiconductor substrate and an element isolation film embedded into the element isolation groove; gate insulating films each formed on corresponding one of the active areas and having a first end portion that overhangs from the corresponding active area onto the element isolation area at one side and a second end portion that overhangs from the corresponding active area onto the element isolation area at the other side, wherein an overhang of the first end portion has a different length from a length of an overhang of the second end portion.
    Type: Grant
    Filed: April 8, 2009
    Date of Patent: March 5, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuhiro Suzuki, Hiroshi Shimode, Takeshi Shimane, Norihisa Arai, Minori Kajimoto
  • Patent number: 8186172
    Abstract: A structure for sensing refrigerant flow rate in a compressor. The structure includes a passage forming member, a restriction hole, a differential pressure-type flow rate sensor, and a partition plate. The compressor includes a housing connected to an external refrigerant circuit via a refrigerant passage. The passage forming member is connected to an outer surface of the housing and forms a part of the refrigerant passage. The restriction hole divides the refrigerant passage into an upstream passage and a downstream passage. The upstream passage is formed in either the housing or the passage forming member. The sensor is provided in the passage forming member and detects pressure in the upstream passage and pressure in the downstream passage to sense flow rate of refrigerant in the refrigerant passage. The partition plate is disposed between the housing and the passage forming member. The restriction hole is formed in the partition plate to extend through the partition plate.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: May 29, 2012
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Yoshinori Inoue, Hirokazu Mesaki, Atsuhiro Suzuki
  • Publication number: 20100327341
    Abstract: A nonvolatile semiconductor memory device includes first electrodes, a second and a third electrode, a first film, a first inter layer film, a second inter layer film, and a second film. The first electrodes each have a charge storage and a control electrode. The second and the third electrodes are formed above the semiconductor substrate. The first film is formed on each sidewall of the second and third electrodes and formed on the surface of the semiconductor substrate. The first inter layer film filled in a gap between the second and third electrodes. The second inter layer film filled in a gap between the first and second electrode. The second film is formed on the first to third gate electrodes, the first film and the first inter layer film, and a second inter layer insulating film to suppress diffusion of hydrogen atoms included in the first inter layer film.
    Type: Application
    Filed: November 13, 2009
    Publication date: December 30, 2010
    Inventor: Atsuhiro SUZUKI
  • Patent number: 7841839
    Abstract: A variable displacement compressor includes a housing assembly. A displacement control structure for the variable displacement compressor includes a passage forming member, a flat partition and a displacement control valve. The passage forming member is connected to an exterior surface of the housing assembly for forming a refrigerant passage for allowing the refrigerant to be discharged out from the compressor to an external refrigerant circuit. The flat partition is interposed between the passage forming member and the housing assembly. A throttle penetrates through the partition, which divides the refrigerant passage into an upstream passage and a downstream passage. The displacement control valve is provided in the passage forming member. The displacement control valve senses pressure of refrigerant in the upstream passage and pressure of the refrigerant in the downstream passage to control flow rate of the refrigerant flowing through a supply passage.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toyota Jidoshokki
    Inventors: Yoshinori Inoue, Atsuhiro Suzuki, Hiroyuki Nakaima
  • Patent number: 7812391
    Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate having a plurality of active regions separately formed by a plurality of trenches formed in a surface of the substrate at predetermined intervals, a first gate insulating film formed on an upper surface of the substrate corresponding to each active region, a gate electrode of a memory cell transistor formed by depositing an electrical charge storage layer formed on an upper surface of the gate insulating film, a second gate insulating film and a control gate insulating film sequentially, an element isolation insulating film buried in each trench and formed from a coating type oxide film, and an insulating film formed inside each trench on a boundary between the semiconductor substrate and the element isolation insulating film, the insulating film containing nontransition metal atoms and having a film thickness not more than 5 ?.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiro Matsuo, Masayuki Tanaka, Atsuhiro Suzuki
  • Patent number: 7812405
    Abstract: A semiconductor device includes a first interlayer insulating film formed above a semiconductor substrate, a first source line formed on the first interlayer insulating film, a second interlayer insulating film formed on the first source line, a plurality of bit lines formed on the second interlayer insulating film so as to extend in a direction, the bit lines being arranged at same width and same width, a third interlayer insulating film formed above the bit lines, a second source line formed on the third interlayer insulating film, and a source shunt line formed between the second and third interlayer insulating films, the source shunt line electrically connecting the first and second source lines to each other, the source shunt line being located between the bit lines so as to extend in the same direction as the bit lines, the source shunt line including a width same as the bit lines.
    Type: Grant
    Filed: August 8, 2007
    Date of Patent: October 12, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Atsuhiro Suzuki