Patents by Inventor Atsuhisa Kageyama

Atsuhisa Kageyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10170081
    Abstract: An image correction device generates a corrected image for a viewer with low vision, by adding excessive emphasis which reduces image quality as perceived by a viewer having normal eyesight, to at least one of luminance gradation, luminance contour, and color tone of a pre-correction image. The image correction device includes: a controller which specifies, in a low vision mode which is an image correction mode for the viewer with low vision, a parameter that represents an amount of correction greater than an upper limit of an amount of correction which does not reduce the image quality as perceived by the viewer having normal eyesight when the pre-correction image is corrected; and an image processor which generates the corrected image by correcting the at least one of the luminance gradation, the luminance contour, and the color tone of the pre-correction image with the amount of correction represented by the parameter.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: SOCIONEXT INC.
    Inventors: Atsuhisa Kageyama, Kazutoshi Funahashi, Shotaro Itakura
  • Publication number: 20170140734
    Abstract: An image correction device generates a corrected image for a viewer with low vision, by adding excessive emphasis which reduces image quality as perceived by a viewer having normal eyesight, to at least one of luminance gradation, luminance contour, and color tone of a pre-correction image. The image correction device includes: a controller which specifies, in a low vision mode which is an image correction mode for the viewer with low vision, a parameter that represents an amount of correction greater than an upper limit of an amount of correction which does not reduce the image quality as perceived by the viewer having normal eyesight when the pre-correction image is corrected; and an image processor which generates the corrected image by correcting the at least one of the luminance gradation, the luminance contour, and the color tone of the pre-correction image with the amount of correction represented by the parameter.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Atsuhisa KAGEYAMA, Kazutoshi FUNAHASHI, Shotaro ITAKURA
  • Patent number: 9386291
    Abstract: In order to obtain an optimum depth enhancement effect for three-dimensional (3D) images, a depth information extractor configured to compute depth information from an input video signal, a 2D/3D converter configured to convert, when the input video signal is a two-dimensional (2D) video signal, the 2D video signal to a first video signal which is a 3D video signal based on the depth information, a correction factor calculator configured to compute a correction factor based on the depth information, a selector configured to select either the input video signal or the first video signal and output the selected signal, and a contour enhancement processor configured to perform an enhancement process on the output of the selector based on the correction factor and output the enhanced signal as an output video signal are provided.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: July 5, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Shinichi Tomioka, Atsuhisa Kageyama, Hiroshi Taniuchi, Shirou Yoshioka
  • Patent number: 8830398
    Abstract: It is determined whether or not an input image is an image converted from an image with a relatively low resolution based on one frame of an image. A resolution determination device includes: an edge strength calculator configured to obtain an edge strength of a pixel included in an input image based on luminance of the pixel and luminance of a pixel adjacent to the pixel, for each of a plurality of pixels included in the input image; and a resolution determiner configured to determine whether or not the input image is an image upconverted from an image with a predetermined resolution or less, based on distribution of the edge strengths.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: September 9, 2014
    Assignee: Panasonic Corporation
    Inventors: Koichi Inoue, Shinichi Tomioka, Atsuhisa Kageyama
  • Publication number: 20140184738
    Abstract: In order to obtain an optimum depth enhancement effect for three-dimensional (3D) images, a depth information extractor configured to compute depth information from an input video signal, a 2D/3D converter configured to convert, when the input video signal is a two-dimensional (2D) video signal, the 2D video signal to a first video signal which is a 3D video signal based on the depth information, a correction factor calculator configured to compute a correction factor based on the depth information, a selector configured to select either the input video signal or the first video signal and output the selected signal, and a contour enhancement processor configured to perform an enhancement process on the output of the selector based on the correction factor and output the enhanced signal as an output video signal are provided.
    Type: Application
    Filed: March 7, 2014
    Publication date: July 3, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shinichi TOMIOKA, Atsuhisa KAGEYAMA, Hiroshi TANIUCHI, Shirou YOSHIOKA
  • Publication number: 20110234622
    Abstract: Complicated adjustment, such as adjusting hue and saturation by varying value for each hue in which hue correction and saturation correction are performed on only an input having a specific value of a specific color component, is performed. In a color space including hue Hi, saturation Si, and value Vi, calculating a hue correction value HVh and a saturation correction value HVs by using the hue Hi and the value Vi as parameters allows the hue correction and the saturation correction to be performed based on the value and completely independently for hue axes of the hue. The correction value calculating circuit scale has no influence on the complexity of the correction. It is possible to calculate the correction values by a certain circuit scale no matter how complicated the correction is.
    Type: Application
    Filed: June 9, 2011
    Publication date: September 29, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Nobuko FUJITA, Shinichi Tomioka, Atsuhisa Kageyama, Takaaki IInuma, Koichi Inoue
  • Publication number: 20100020243
    Abstract: In a video signal processor (10), a video signal is given to a video input terminal (101) via a coupling capacitor (200). A clamp circuit (104) clamps the video signal input via the video input terminal (101). A format detector section (105) detects a format of the video signal. A controller section (107) changes power supply capability of the clamp circuit (104) according to a detection result of the format detector section (105).
    Type: Application
    Filed: September 9, 2008
    Publication date: January 28, 2010
    Inventors: Katsuyuki Kitano, Keiichi Kuzumoto, Atsuhisa Kageyama
  • Publication number: 20080158033
    Abstract: A driving device for driving an image display system, which sequentially receives input image data corresponding to gradation of each pixel of a display image and outputs a driving voltage signal includes: an operation section for obtaining output image data of which a bit number is smaller than a bit number of the input image data based on input image data of a target pixel to be processed and input image data of a pixel in vicinity of the target pixel; a reference voltage generation section for generating a plurality of reference voltages of different levels; and a reference voltage selection section for selecting one of the plurality of reference voltages. The operation section is configured to obtain output image data of the target pixel so that a difference between the input image data and output image data of the target pixel and a difference between the input image data and output image data of the pixel in vicinity of the target pixel cancel out each other.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 3, 2008
    Inventors: Yasuyuki Doi, Makoto Hattori, Hisao Kunitani, Atsuhisa Kageyama, Tetsuro Oomori, Osamu Sarai, Tooru Suyama, Kurumi Nakayama, Kazuya Matsumoto
  • Patent number: 7259599
    Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: August 21, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hisao Kunitani, Satoru Tanigawa, Hiroshi Sonobe, Atsuhisa Kageyama
  • Patent number: 7209182
    Abstract: A false contour correcting apparatus is capable of removing a false contour in an image based on a digital image signal while avoiding such a side effect caused by false contour correction where noises negatively effecting the display occur on a screen. Therefore, in the false contour correcting apparatus according, a double bit change detection circuit detects as a double bit change a signal value change which is twice a minimum quantization unit in a digital image signal, and outputs a double bit change detection signal representing the position of the double bit change. A signal correction circuit corrects the double bit change in the digital image signal into two one-bit changes on the basis of the double bit change detection signal. Consequently, a false contour corresponding to a portion where the double bit change exists is removed.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: April 24, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kawabata, Atsuhisa Kageyama, Masahiro Takeshima
  • Patent number: 7113227
    Abstract: The present invention has an object to provide a gradation correcting apparatus for correcting the gradation of the white side of a video luminance signal. The gradation correcting apparatus is provided with a maximum value detector 101 for detecting a maximum value of a luminance signal S101, a white comparator 102 for comparing the luminance signal S101, a maximum luminance value S111 detected by the maximum value detector 101, and a first white threshold value S103, a white linear converter 103 for performing linear conversion on the luminance signal S101 on the basis of the maximum luminance value S111, the first white threshold value S103, and a second white threshold value S104, and a white controller 104 for correcting the luminance signal S101 on the basis of the result of the comparison in the white comparator 102, the output of the white linear converter 103, and the second white threshold value S104.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: September 26, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuki Kakuya, Atsuhisa Kageyama, Katsuya Ishikawa, Hidetoshi Suzuki
  • Publication number: 20060146891
    Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells stepwisely to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. According to the semiconductor device of the present invention, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.
    Type: Application
    Filed: November 19, 2004
    Publication date: July 6, 2006
    Inventors: Hisao Kunitani, Satoru Tanigawa, Hiroshi Sonobe, Atsuhisa Kageyama
  • Patent number: 7046298
    Abstract: This invention provides a data signal extraction apparatus that accurately extracts data from a data signal that is serially transmitted even when phase shift or the like occurs. According to this apparatus, a phase shift amount calculation circuit 13 calculates a phase shift amount S13, then a correction amount calculation circuit 14 calculates a correction amount S14 on the basis of the phase shift amount S13, an extraction interval correction circuit 10 corrects an extraction interval value S9 on the basis of the correction amount, and an extraction pulse generation circuit 11 generates an extraction pulse S11 on the basis of a corrected extraction interval value S10, thereby extracting data from a binary signal S8 on the basis of the extraction pulse.
    Type: Grant
    Filed: March 28, 2003
    Date of Patent: May 16, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Kuzumoto, Toshihiro Matsumura, Akihiro Suzuki, Atsuhisa Kageyama
  • Patent number: 7034896
    Abstract: The present invention provides a gradation correction device which can perform gradation correction using digital feedback processing, and furthermore, can control the digital feedback processing with high accuracy. The gradation correction device is provided with a correction gain adjustable amount generation circuit (103) and a correction gain generation circuit (104), and the correction gain adjustable amount generation circuit (103) obtains a correction gain adjustable amount which is non-linear in relation to a difference S between a reference luminance level Yb1 and a maximum luminance level, and greater gamma correction is carried out as the value of the difference is larger.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: April 25, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keiichi Ito, Atsuhisa Kageyama
  • Patent number: 6967692
    Abstract: A luminance signal processing apparatus that detects an average luminance level, adaptively to various video signal formats.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: November 22, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yuki Kakuya, Atsuhisa Kageyama, Nobutaka Okada, Keiichi Ito
  • Patent number: 6903781
    Abstract: A video signal processing apparatus comprises a sub-screen processing integrated circuit for subjecting a sub-screen video signal to scale-down processing to reduce its display region and output the sub-screen video signal, and a main-screen processing integrated circuit comprising: a switching circuit for receiving a main-screen video signal and the scaled-down sub-screen video signal which is outputted from the sub-screen processing integrated circuit, and selecting the main-screen video signal for a main-screen display region while selecting the sub-screen video signal for a sub-screen display region; an A/D conversion circuit for converting the video signal outputted from the switching circuit into a digital video signal; a digital signal processing circuit for digitally processing the digital video signal outputted from the A/D conversion circuit; and a D/A conversion circuit for converting the digitally-processed video signal into an analog video signal.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: June 7, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Satoru Tanigawa, Atsuhisa Kageyama, Ryuichi Shibutani
  • Publication number: 20040008282
    Abstract: A false contour correcting apparatus is capable of removing a false contour in an image based on a digital image signal while avoiding such a side effect caused by false contour correction where noises negatively effecting the display occur on a screen. Therefore, in the false contour correcting apparatus according, a double bit change detection circuit detects as a double bit change a signal value change which is twice a minimum quantization unit in a digital image signal, and outputs a double bit change detection signal representing the position of the double bit change. A signal correction circuit corrects the double bit change in the digital image signal into two one-bit changes on the basis of the double bit change detection signal. Consequently, a false contour corresponding to a portion where the double bit change exists is removed.
    Type: Application
    Filed: July 11, 2003
    Publication date: January 15, 2004
    Inventors: Minoru Kawabata, Atsuhisa Kageyama, Masahiro Takeshima
  • Patent number: 6661469
    Abstract: A false contour correcting apparatus is capable of removing a false contour in an image based on a digital image signal while avoiding such a side effect caused by false contour correction where noises negatively effecting the display occur on a screen. Therefore, in the false contour correcting apparatus according, a double bit change detection circuit detects as a double bit change a signal value change which is twice a minimum quantization unit in a digital image signal, and outputs a double bit change detection signal representing the position of the double bit change. A signal correction circuit corrects the double bit change in the digital image signal into two one-bit changes on the basis of the double bit change detection signal. Consequently, a false contour corresponding to a portion where the double bit change exists is removed.
    Type: Grant
    Filed: June 15, 2000
    Date of Patent: December 9, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Minoru Kawabata, Atsuhisa Kageyama, Masahiro Takeshima
  • Patent number: 6636229
    Abstract: A gradation correction circuit comprises: an arithmetic means (101˜104, 106, 108˜110) for operating an output value corresponding to each broken point of a broken line in a vertical blanking period; a level detection circuit 107 for identifying a size relation between each broken line point which is an input value corresponding to each broken point and an input video signal, and calculating a difference between the input video signal and each broken line point; and a correction means (101˜102, 104, 107, 109˜111) for selecting a gradient of the broken line on the basis of the result identified by the level detection circuit 107, and performing gradation correction of the input video signal on the basis of the selected gradient of the broken line, the output value calculated by the arithmetic means, and the difference calculated by the level detection circuit, wherein the arithmetic means and the correction means share a number of circuits (102, 109, 110).
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: October 21, 2003
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Katsuya Ishikawa, Atsuhisa Kageyama, Keiichi Ito
  • Patent number: RE38413
    Abstract: Red color saturation is increased and red color with higher purity can be reproduced by composing: a red color detection circuit 1 for detecting a red color signal having higher purity by inputting color differential signals (R-Y) and (B-Y) modulated by color subcarrier, subtracting the absolute value of the (B-Y) signal from the positive polarity component of the (R-Y) signal and removing the negative part of the subtracted signal; Y signal compensation block including: first gain controller 50b for controlling the output signal amplitude of red color detection circuit 1 and a subtracter 50a for subtracting the output signal of first gain controller 50b from a luminance signal Y; an (R-Y) signal compensation block including: second gain controller 51b for controlling the output signal amplitude of red color detection circuit 1 and an adder 51a for adding the output signal of second gain controller 51b and the input (R-Y) signal; and a (B-Y) signal compensation block including: third gain controller 52b for c
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: February 3, 2004
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Hiroko Sugimoto, Atsuhisa Kageyama, Masahiro Takeshima, Minoru Kawabata