Patents by Inventor Atsuki Matsumura

Atsuki Matsumura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8043929
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 25, 2011
    Assignee: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Publication number: 20080268613
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Application
    Filed: May 14, 2008
    Publication date: October 30, 2008
    Applicant: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried von Ammon
  • Patent number: 7320925
    Abstract: A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region. A method for the production of an SOI substrate, includes forming on the surface of a semiconductor substrate made of a silicon single crystal a protective film designated to serve as a mask for ion implantation, forming an opening part of a stated pattern in the protective film, implanting oxygen ions into the surface of the semiconductor substrate in a direction not perpendicular thereto, and heat treating the semiconductor substrate thereby forming a buried oxide film in the semiconductor substrate, and inducing at the step of implanting oxygen ions into the surface of the semiconductor substrate the impartation of at least two angles to be formed between the projection of the flux of implantation of oxygen ions and a specific azimuth of the main body of the substrate.
    Type: Grant
    Filed: June 2, 2004
    Date of Patent: January 22, 2008
    Assignee: Siltronic AG
    Inventors: Tsutomu Sasaki, Seiji Takayama, Atsuki Matsumura
  • Patent number: 7204887
    Abstract: The present invention provides a wafer holder, a wafer support member, a wafer boat and a heat treatment furnace, which are capable of sufficiently suppressing slip dislocations, without lowering productivity and at low cost, in the high temperature heat treatment of silicon wafers, and said wafer holder is characterized in that: the wafer holder is composed of a wafer support plate and three or more wafer support members mounted on said wafer support plate, each of the wafer support members having a wafer support portion or more; at least one of said wafer support members is a tilting wafer support member which has a plurality of upward-convex wafer support portions on the upper surface and is tiltable with respect to said wafer support plate; and the wafer is supported by at least four wafer support portions.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: April 17, 2007
    Assignee: Nippon Steel Corporation
    Inventors: Keisuke Kawamura, Tsutomu Sasaki, Atsuki Matsumura, Atsushi Ikari, Isao Hamaguchi, Yoshiharu Inoue, Koki Tanaka, Shunichi Hayashi
  • Patent number: 7084459
    Abstract: There is provided an SOI substrate having an SOI structure with an insulating layer and a surface single crystal silicon layer successively formed on a single crystal wafer, the SOI substrate having no pit generation in the SOI layer, being producible at low cost and at high productivity and having excellent gettering capacity, wherein the SOI substrate contains nitrogen and carbon with a nitrogen content of no greater than 1×1016 atoms/cm3 and a carbon content of no greater than 1×1018 atoms/cm3.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: August 1, 2006
    Assignee: Nippon Steel Corporation
    Inventors: Tsutomu Sasaki, Isao Hamaguchi, Atsuki Matsumura
  • Patent number: 7067402
    Abstract: A Separation by Implanted Oxygen (“SIMOX”) substrate and method for making thereof are provided. The SIMOX substrate can be produced by employing an oxygen ion implantation amount in a low dose range. The substrate is a high quality SOI substrate having an increased thickness of a BOX layer. More specifically, the SIMOX substrate and method for making the same are provided such that a buried oxide layer and a surface silicon layer are formed by applying the implantation of oxygen ions in a silicon substrate and a high temperature heat treatment thereafter. A buried oxide layer is provided by applying a high temperature heat treatment after an oxygen ion implantation; then applying an additional oxygen ion implantation so that the peak position of the distribution of implanted oxygen is located at a portion lower than the interface between the buried oxide layer, already formed, and the substrate thereunder. Then, another high temperature heat treatment is applied.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: June 27, 2006
    Assignee: Nippon Steel Corporation
    Inventors: Atsuki Matsumura, Keisuke Kawamura, Yoichi Nagatake, Seiji Takayama
  • Publication number: 20050139961
    Abstract: Hetero-semiconductor structures possessing an SOI structure containing a silicon-germanium mixed crystal are produced at a low cost and high productivity. The semiconductor substrates comprise a first layer formed of silicon having germanium added thereto, a second layer formed of an oxide and adjoined to the first layer, and a third layer derived from the same source as the first layer, but having an enriched content of germanium as a result of thermal oxidation and thinning of the third layer.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 30, 2005
    Applicant: Siltronic AG
    Inventors: Josef Brunner, Hiroyuki Deai, Atsushi Ikari, Martin Grassl, Atsuki Matsumura, Wilfried Ammon
  • Publication number: 20040253793
    Abstract: A method is for commercially producing by the SIMOX technique a perfect partial SOI structure avoiding exposure of a buried oxide film through the surface thereof and forming no step between an SOI region and a non-SOI region.
    Type: Application
    Filed: June 2, 2004
    Publication date: December 16, 2004
    Applicant: Siltronic AG
    Inventors: Tsutomu Sasaki, Seiji Takayama, Atsuki Matsumura
  • Publication number: 20040171228
    Abstract: The present invention provides a SIMOX substrate produced by employing an oxygen ion implantation amount in a low dose range, which substrate is a high quality SOI substrate having an increased thickness of a BOX layer, and a method of producing the same, and more specifically, provides a method of producing a SIMOX substrate wherein a buried oxide layer and a surface silicon layer are formed by applying the implantation of oxygen ions in a silicon substrate and a high temperature heat treatment thereafter, characterized by: forming the buried oxide layer through applying a high temperature heat treatment after an oxygen ion implantation; then applying an additional oxygen ion implantation so that the peak position of the distribution of implanted oxygen is located at a portion lower than the interface between the buried oxide layer, already formed, and the substrate thereunder; and then applying another high temperature heat treatment, and a SIMOX substrate produced by said method having a surface silicon la
    Type: Application
    Filed: September 29, 2003
    Publication date: September 2, 2004
    Inventors: Atsuki Matsumura, Keisuke Kawamura, Yoichi Nagatake, Seiji Takayama
  • Patent number: 6767801
    Abstract: A SIMOX substrate having a buried oxide layer and a surface single crystal silicon layer formed therein is produced by a method which comprises implanting oxygen ions into a silicon single crystal substrate and subsequently performing a heat treatment at an elevated temperature on the substrate. The method is characterized by performing the former stage of the heat treatment at a temperature of not lower than 1150° C. and lower than the melting point of single crystal silicon in an atmosphere obtained by adding oxygen under a partial pressure of not more than 1% to an inert gas and subsequently performing at least part of the latter stage of the heat treatment by increasing the partial pressure of oxygen within a range in which no internal oxidation is suffered to occur in the buried oxide layer. It can also be prepared by performing the former stage of the high temperature heat treatment at a temperature of not lower than 1150° C.
    Type: Grant
    Filed: September 9, 2002
    Date of Patent: July 27, 2004
    Assignee: Nippon Steel Corporation
    Inventors: Keisuke Kawamura, Atsuki Matsumura, Toshiyuki Mizutani
  • Patent number: 6740565
    Abstract: There is provided a process for fabrication of a SIMOX substrate wherein oxygen ions are implanted into a single crystal silicon substrate and then subjected to a high-temperature heat treatment to form a buried oxide layer and a surface single crystal silicon layer, wherein the single crystal silicon substrate used has a mean resistivity of 100 &OHgr;cm or greater, and there is conducted a step of maintaining a temperature of from 800° C. to 1250° C. for a predetermined time in the final stage of the high-temperature heat treatment, as well as a SIMOX substrate wherein the mean resistivity of the substrate obtained by the process is 100 &OHgr;cm or greater.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: May 25, 2004
    Assignee: Nippon Steel Corporation
    Inventors: Atsuki Matsumura, Tsutomu Sasaki, Koichi Kitahara
  • Publication number: 20040018363
    Abstract: There is provided an SOI substrate having an SOI structure with an insulating layer and a surface single crystal silicon layer successively formed on a single crystal wafer, the SOI substrate having no pit generation in the SOI layer, being producible at low cost and at high productivity and having excellent gettering capacity, wherein the SOI substrate contains nitrogen and carbon with a nitrogen content of no greater than 1×1016 atoms/cm3 and a carbon content of no greater than 1×1016 atoms/cm3.
    Type: Application
    Filed: January 29, 2003
    Publication date: January 29, 2004
    Inventors: Tsutomu Sasaki, Isao Hamaguchi, Atsuki Matsumura
  • Publication number: 20030170940
    Abstract: There is provided a process for fabrication of a SIMOX substrate wherein oxygen ions are implanted into a single crystal silicon substrate and then subjected to a high-temperature heat treatment to form a buried oxide layer and a surface single crystal silicon layer, wherein the single crystal silicon substrate used has a mean resistivity of 100 &OHgr;cm or greater, and there is conducted a step of maintaining a temperature of from 800° C. to 1250° C. for a predetermined time in the final stage of the high-temperature heat treatment, as well as a SIMOX substrate wherein the mean resistivity of the substrate obtained by the process is 100 &OHgr;cm or greater.
    Type: Application
    Filed: November 26, 2002
    Publication date: September 11, 2003
    Inventors: Atsuki Matsumura, Tsutomi Sasaki, Koichi Kitahara
  • Patent number: 6617034
    Abstract: A SOI substrate of high quality which allows LSI to be formed thereon in an improved yield and realizes excellent electric properties and a method for the production thereof are provided. The SOI substrate is obtained by forming an embedded oxide layer on a silicon single crystal substrate and forming a SOI layer for the formation of a device on the embedded oxide layer and is characterized by the SOI layer containing pit-like defects at a density of not more than 5 cm−2 or the embedded oxide layer containing pinhole defects at a density of less than one piece/cm2.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: September 9, 2003
    Assignee: Nippon Steel Corporation
    Inventors: Isao Hamaguchi, Atsushi Ikari, Atsuki Matsumura, Keisuke Kawamura, Takayuki Yano, Yoichi Nagatake
  • Publication number: 20030036289
    Abstract: A SIMOX substrate having a buried oxide layer and a surface single crystal silicon layer formed therein is produced by a method which comprises implanting oxygen ions into a silicon single crystal substrate and subsequently performing a heat treatment at an elevated temperature on the substrate. The method is characterized by performing the former stage of the heat treatment at a temperature of not lower than 1150° C. and lower than the melting point of single crystal silicon in an atmosphere obtained by adding oxygen under a partial pressure of not more than 1% to an inert gas and subsequently performing at least part of the latter stage of the heat treatment by increasing the partial pressure of oxygen within a range in which no internal oxidation is suffered to occur in the buried oxide layer. It can also be prepared by performing the former stage of the high temperature heat treatment at a temperature of not lower than 1150° C.
    Type: Application
    Filed: September 9, 2002
    Publication date: February 20, 2003
    Inventors: Keisuke Kawamura, Atsuki Matsumura, Toshiyuki Mizutani
  • Publication number: 20030029570
    Abstract: The present invention provides a wafer holder, a wafer support member, a wafer boat and a heat treatment furnace, which are capable of sufficiently suppressing slip dislocations, without lowering productivity and at low cost, in the high temperature heat treatment of silicon wafers, and said wafer holder is characterized in that: the wafer holder is composed of a wafer support plate and three or more wafer support members mounted on said wafer support plate, each of the wafer support members having a wafer support portion or more; at least one of said wafer support members is a tilting wafer support member which has a plurality of upward-convex wafer support portions on the upper surface and is tiltable with respect to said wafer support plate; and the wafer is supported by at least four wafer support portions.
    Type: Application
    Filed: June 14, 2002
    Publication date: February 13, 2003
    Inventors: Keisuke Kawamura, Tsutomu Sasaki, Atsuki Matsumura, Atsushi Ikari, Isao Hamaguchi, Yoshiharu Inoue, Koki Tanaka, Shunichi Hayashi
  • Patent number: 5753935
    Abstract: In a radiation detection device using superconducting tunnel junctions, the increase in electric capacitance and the decrease in electric resistance due to the increase in junction area for improvement of the detection efficiency are largely repressed by the invention. The junctions are connected in series. The number of the series-connected junctions is settled in the range of larger than 0.05 (SC.sub.o /C')0.5 and smaller than 20 (SC.sub.o /C')0.5 or 10SCo/C', whichever is larger, where S is the total area of the junctions, cm.sup.2, C.sub.o is the electric capacitance per unit area of the junctions, F/cm.sup.2, and C' is the electric capacitance connected to the device in parallel so as to transfer and amplify the signals from the device, F.
    Type: Grant
    Filed: December 23, 1992
    Date of Patent: May 19, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Atsuki Matsumura, Tooru Takahashi
  • Patent number: 5710437
    Abstract: A radiation detecting device including a superconducting tunnel junction having a three-layer structure formed by depositing a lower electrode, a tunnel barrier layer, and an upper electrode in sequence. The upper electrode, the tunnel barrier layer and lower electrode have substantially aligned side walls around substantially their entire perimeters such that a cross-section of the three-layer structure along a path perpendicular to a direction of the deposition is substantially constant in shape and size along the direction of the deposition and such that no portion of the lower electrode or the upper electrode extends beyond the tunnel barrier layer. At least one of the upper electrode and the lower electrode is made of superconducting material.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: January 20, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Toru Takahashi, Atsuki Matsumura
  • Patent number: 5321276
    Abstract: A superconducting tunnel junction radiation sensing device includes first and second superconductor electrodes and a tunnel barrier layer interposed therebetween. The tunnel barrier layer is made up of a thin-wall portion and a thick-wall portion each formed of a semiconductor or an insulator, and each having opposite surfaces respectively contacting the first and second superconductor electrodes, and each extending adjacent each other in a same horizontal plane between the first and second electrodes. The thick-wall portion has a vertical thickness which is at least twice that of the thin-wall portion. Furthermore, the thickness of the thin-wall portion is such that a tunnel effect is enabled therethrough form the first electrode to the second electrode, and the thickness of the thick-wall portion is such that a tunnel effect is substantially prohibited therethrough from the first electrode to the second electrode.
    Type: Grant
    Filed: October 1, 1991
    Date of Patent: June 14, 1994
    Assignee: Nippon Steel Corporation
    Inventors: Masahiko Kurakado, Atsuki Matsumura, Takeshi Kaminaga, Tooru Takahashi