Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.

Abstract: A technique is provided which can facilitate management of data in a memory device in a semiconductor device including the memory device and a data processing device. The semiconductor device includes a first external terminal, a second external terminal, a data processing device, and a memory device. The semiconductor device further includes a first bus coupled between the data processing device and the memory device, a second bus coupled between the data processing device and the second external terminal, a third bus coupled to the first external terminal, and a control circuit coupled to the first bus and the third bus. The control circuit has a management function of the memory device using the third bus.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.

Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.

Abstract: A semiconductor device includes a first semiconductor chip located over a substrate; and a second semiconductor chip located over the first semiconductor chip, wherein the first semiconductor chip includes a first internal power supply generation circuit that generates a first internal power supply voltage supplied to a first internal circuit; a first penetration electrode formed from an upper surface of the first semiconductor chip to an underside of the first semiconductor chip and electrically connected to the first internal power supply generation circuit; a first reference voltage generation circuit that generates a first reference voltage; and a second penetration electrode formed from the upper surface of the first semiconductor chip to the underside of the first semiconductor chip and electrically connected to the first reference voltage generation circuit.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11_1 and a second memory area 11_2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm_ are disposed in a boundary area 18 between the first and second memory areas 11_1 and 11_2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . , BLm— are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: An object of the invention is to make effective use of the structure of a multilayered semiconductor device that uses penetration electrodes in such a manner that the layered chips obtain stable internal power supply voltages with no increase in current consumption or in the area of the layered chips. Internal power supply generation circuits furnished in each of the layered core chips have their outputs commonly coupled via electrodes penetrating the layered core chips. This allows electrical charges to be shared among the core chips, optimizes internal power consumption of the multilayered semiconductor device as a whole, and inhibits fluctuations in the internal power supply voltages.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units. A first bus for transfer of address/control signals, includes a first buffer circuit operating as a pipeline register. A second bus for bidirectional transfer of write/read data, includes a second buffer circuit operating as a pipeline register. A first control circuit sequentially sends the address/control signals on the first bus, and a second control circuit sequentially sends/receives write/read data on the second bus.

Abstract: A semiconductor storage device 1 according to an aspect includes a first memory area 11—1 and a second memory area 11—2. Memory cells MC_m_n and bit lines BL1, BL2_, . . . . , BLm_are disposed in a boundary area 18 between the first and second memory areas 11—1 and 11—2. The memory cells MC_m_n disposed in the boundary area 18 includes memory cells into which no data is written, and a line 56 is formed in a place that overlaps memory cells disposed in the boundary area 18 when the boundary area 18 is viewed from the top. As a result, it is possible to increase the integration density of a memory cell array and provide a line in the memory cell array.

Abstract: A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area.

Abstract: A semiconductor storage device includes: a plurality of memory cell arrays; a plurality of bidirectional data buses provided in correspondence with respective ones of the plurality of memory cell arrays; a plurality of bidirectional buffer circuits, which are provided in correspondence with respective ones of the memory cell arrays, capable of connecting adjacent bidirectional data buses serially so as to relay data in the bidirectional data buses; and a control circuit for controlling activation of the bidirectional buffer circuits. The bidirectional buffer circuit is arranged so as to invert logic and the bidirectional buffer circuit is arranged so as not to invert logic.

Abstract: A semiconductor device includes a memory cell array including a plurality of memory array basic units, a first bus for transfer of address/control signals, including a first buffer circuit operating as a pipeline register, a second bus for bidirectional transfer of write/read data, including a second buffer circuit operating as a pipeline register, a first control circuit sequentially sending the address/control signals on the first bus, and a second control circuit sequentially sending/receiving write/read data on the second bus (FIG. 11).

Abstract: A semiconductor apparatus includes a programmable logic chip configured to output a control signal, and a memory chip coupled to the programmable logic chip. The memory chip includes a plurality of memory cores, a plurality of bus-interface circuits each configured to couple with the memory cores, and a selection circuit configured to couple the memory cores with one of the bus-interface circuits in response to a predetermined logic level of the control signal.

Abstract: A semiconductor device includes a bidirectional first bus arranged in common for a plurality of memory array basic units transferring write data and read data, a second bus transferring address/command, a plurality of first buffer circuits receiving addresses/command transferred to the second bus, wherein a control delay for generating the address/command and preparing write data to the first bus for write access and an output delay for outputting read data are both set to a length greater than or equal to a selection time for writing or reading of data to a memory cell of a selected area.