Patents by Inventor Atsuo Inoue

Atsuo Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030155859
    Abstract: A method of manufacturing a field emission device having emitter shapes, comprise the steps of forming a first original plate having a major surface provided with emitter shapes, by cutting a surface portion of a base material, forming a first material layer on the major surface of the first original plate on which the emitter shapes are provided; separating the first material layer from the first original plate, thereby obtaining a second original plate having recesses onto which the emitter shapes on the first original plate are transferred, forming a second material layer on a major surface of the second original plate on which the recesses are provided; and separating the second material layer from the second original plate, thereby to obtain a substrate having projections portions onto which shapes of the recesses of the second original plate are transferred.
    Type: Application
    Filed: February 27, 2003
    Publication date: August 21, 2003
    Inventors: Masayuki Nakamoto, Atsuo Inoue
  • Publication number: 20030136138
    Abstract: An air conditioner for a vehicle uses a hybrid compressor (4) including a first compression mechanism driven by a first drive source (2) and a second compression mechanism driven by a second drive source (5), and a single discharge port connected to the first and the second compression mechanisms. The operation of the hybrid compressor is controlled by a controller (15) in accordance with a control mode. The controller has a first operation mode in which the first compression mechanism alone is driven, a second operation mode in which the second compression mechanism alone is driven, a third operation mode in which the first and the second compression mechanisms are simultaneously driven, and a fourth operation mode in which the first and the second compression mechanisms are simultaneously stopped. Depending upon various conditions, the controller selects, as the control mode, one of the first, the second, the third, and the fourth operation modes.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 24, 2003
    Inventors: Masato Tsuboi, Atsuo Inoue, Kenichi Suzuki, Tomonori Imai
  • Publication number: 20030039313
    Abstract: In a controller device, when a first transmitting signal is at a “L” level, a first operation voltage is high and the amplitude of signals CK and ICK is large, and on the contrary, the amplitude is small when the first transmitting signal is at a “H” level. In a data carrier device, the signals CK and ICK are subjected to full-wave rectification by a rectifier circuit so as to generate a second operation voltage, and a first receiving signal is extracted from the second operation voltage by a first signal detection circuit. On the other hand, in the data carrier device, when a second transmitting signal is at a “L” level, impedance between two contacts is small and the amplitude of the signals CK and ICK is small, and on the contrary, the amplitude is large when the second transmitting signal is at a “H” level. In the controller device, change of the amplitude of the signal ICK is extracted as a second receiving signal by a second signal detection circuit.
    Type: Application
    Filed: August 20, 2002
    Publication date: February 27, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Atsuo Inoue, Shota Nakashima
  • Patent number: 6468875
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: January 24, 2001
    Date of Patent: October 22, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6333528
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: December 25, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6294438
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: June 8, 2000
    Date of Patent: September 25, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Publication number: 20010019874
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Application
    Filed: January 24, 2001
    Publication date: September 6, 2001
    Applicant: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6214660
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: October 23, 1998
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6204111
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: March 20, 2001
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Uemoto, Eiji Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 6169304
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 1021 atoms/cm3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 2, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6126752
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 9, 1997
    Date of Patent: October 3, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6107657
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: August 22, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 6080617
    Abstract: A semiconductor device comprising an integrated circuit and a capacitor. In this capacitor, a bottom electrode, a dielectric film and a top electrode are formed, independently of the integrated circuit, on the interlayer insulating film, and the top electrode and bottom electrode are connected with metal interconnections through contact holes opened in the protective film for protecting the surface of the capacitor. In this constitution, either the top electrode or the bottom electrode is connected the bias line of the integrated circuit, and the other is connected to the ground line, so that extraneous emission may be reduced without having to connect the capacitor outside.
    Type: Grant
    Filed: October 15, 1997
    Date of Patent: June 27, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Shinitirou Hayashi, Tooru Nasu, Koichi Arita, Atsuo Inoue, Akihiro Matsuda, Masaki Kibe, Tatsuo Ootsuki
  • Patent number: 6033920
    Abstract: This invention relates to a semiconductor device with embedded capacitor elements of which capacitor insulation layer is made of ferroelectric layer or dielectric layer of high dielectric constant, and its manufacturing method. This invention is made in order to solve the problems of rapid increase of leak current of capacitor element and the poor reliability caused by the large deviation of crystal sizes of conventional capacitor insulation layer of capacitor element incorporated in the semiconductor device.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: March 7, 2000
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Shimada, Yasuhiro Uemoto, Atsuo Inoue, Taketoshi Matsuura, Masamichi Azuma
  • Patent number: 6016966
    Abstract: In an air conditioning system for controlling the temperature of a vehicle passenger compartment, a valve is disposed in a fluid passageway for controlling an amount of the engine coolant flowing toward the heat exchanger. A sensor device senses an air temperature for the air flow through the heat exchanger and generates an electrical sensor signal indicative thereof. A temperature selector selects a target temperature of the air flow through the heat exchanger and generates an electrical set signal indicative thereof. A control circuit controls opening of the valve by integrating a feed-back control and a feed-forward control based on the electrical sensor signal and the electrical set signal.
    Type: Grant
    Filed: August 26, 1997
    Date of Patent: January 25, 2000
    Assignee: Sanden Corporation
    Inventor: Atsuo Inoue
  • Patent number: 6015987
    Abstract: A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm.sup.3 or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10.sup.21 atoms/cm.sup.3 or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.
    Type: Grant
    Filed: May 4, 1998
    Date of Patent: January 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Koji Arita, Eiji Fujii, Yasuhiro Shimada, Yasuhiro Uemoto, Toru Nasu, Akihiro Matsuda, Yoshihisa Nagano, Atsuo Inoue, Taketoshi Matsuura, Tatsuo Otsuki
  • Patent number: 5943568
    Abstract: A method of making a semiconductor device include forming: (a) a semiconductor substrate on whose surface an integrated circuit is formed, (b) a first insulating layer on the semiconductor device and having first contact holes which lead to the integrated circuit, (c) a capacitance element on the first insulating layer, (d) a second insulating layer on the first insulating layer to cover the capacitance element, and having second contact holes which lead to an upper and a lower electrodes of the capacitance element respectively, and (e) interconnections which are connected to the integrated circuit and the capacitance element respectively through the first and second contact holes. The hydrogen density of this semiconductor device is 10.sup.11 atoms/cm.sup.2 or less.
    Type: Grant
    Filed: March 5, 1997
    Date of Patent: August 24, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Eiji Fujii, Atsuo Inoue, Koji Arita, Toru Nasu, Akihiro Matsuda
  • Patent number: 5929475
    Abstract: A method for fabricating a capacitor for an integrated circuit, comprising the steps of forming a titanium film for an adhesion layer over a substrate, forming a titanium dioxide film for a diffusion barrier layer by annealing the titanium film after ion-implantation of oxygen ion into a surface region of the titanium film so as to change titanium in the surface region to titanium dioxide, and forming a high dielectric constant capacitor on the titanium dioxide film.
    Type: Grant
    Filed: December 15, 1995
    Date of Patent: July 27, 1999
    Inventors: Yasuhiro Uemoto, Eigi Fujii, Koji Arita, Yoshihisa Nagano, Yasuhiro Shimada, Masamichi Azuma, Atsuo Inoue, Yasufumi Izutsu
  • Patent number: 5920574
    Abstract: A method for an accelerated test of semiconductor devices comprises the steps of determining a relational expression t.sub.1 =t.sub.2.sup.m between an information holding lifetime t.sub.1 at a temperature T.sub.1 and another lifetime t.sub.2 at another temperature T.sub.2, expressing the exponent m as a function of the temperature that is proportional to the Boltzmann's factor, and calculating the information holding lifetime t.sub.2 at the temperature T.sub.2 on the basis of the information holding lifetime t.sub.1 at the temperature T.sub.1 using the relational expression.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: July 6, 1999
    Assignee: Matsushita Electronics Corporation
    Inventors: Yasuhiro Shimada, Keisaku Nakao, Atsuo Inoue, Masamichi Azuma, Eiji Fujii
  • Patent number: 5837591
    Abstract: A semiconductor device comprises silicon substrate 1 on which an integrated circuit is formed, first insulating layer 6 formed on silicon substrate 1, a capacitor comprising lower electrode 7 formed on first insulating layer 6, dielectric film 8 having a high dielectric constant and upper electrode 9, a second insulating film 11 having contact holes 13 which lead to lower electrode 7 and upper electrode 9 independently, diffusion barrier layer 17 which touches lower electrode 7 and upper electrode 9 at bottom of contact holes 13, and interconnection layer 15 formed on diffusion barrier layer 17. In diffusion barrier layer 17 at the bottom of contact hole 13, a lamellar region made of granular crystal is formed.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: November 17, 1998
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Shimada, Atsuo Inoue, Koji Arita, Toru Nasu, Yoshihisa Nagano, Akihiro Matsuda