Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information.

Abstract: A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

Abstract: A system, includes a controller including a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,

Abstract: A semiconductor device includes a first input terminal receiving a termination resistance control signal, and a termination resistance circuit that is able to be controlled to be turned on or off by the termination resistance control signal. The termination resistance circuit is turned off, irrespective of a level of said termination resistance control signal when the semiconductor device outputs data in response to a read command.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command, a clock signal and an address, and communicate a data, and communicate a strobe signal related to the data, and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, one of the plurality of first external terminals and one of the plurality of second external terminals transferring an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data,

Abstract: A memory system includes a plurality of semiconductor memory devices each including a termination resistance circuit that can be controlled to be turned on or off from an outside by a termination resistance control signal, and a memory controller. The memory controller includes a termination resistance control unit that outputs the termination resistance control signal so that when a read command or a write command is executed on one of the semiconductor memory devices, termination resistances of all of the semiconductor memory devices are turned on, and when any of the semiconductor memory devices does not execute the read command or the write command, the termination resistances of all of the semiconductor memory devices are turned off. The termination resistance circuit of one of the semiconductor memory devices is turned off, irrespective of the level of the termination resistance control signal when the one of the semiconductor memory devices outputs data in response to the read command.

Abstract: A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble resister configured to be capable of storing the information.

Abstract: A semiconductor memory device, includes a clock terminal provided to receive a clock signal, a data terminal provided to transfer a data therethrough in synchronization with the clock signal, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough, a command terminal provided to receive a command that communicates the data with an outside thereof, and an address terminal provided to be supplied an information specifying a length of a preamble of the strobe signal from an outside of the semiconductor memory device, prior to communicating the data.

Abstract: A semiconductor memory device, includes a data terminal provided to transfer a data therethrough, a strobe terminal provided to be related in the data terminal and to transfer a strobe signal therethrough a command terminal provided to receive a command that communicates the data with an outside thereof, and a preamble resister configured to be capable of specifying a length of a preamble of the strobe signal prior to the communicating.

Abstract: A controller, includes a plurality of external terminals configured to supply a command and an address to a semiconductor memory device, communicate a data with the semiconductor memory device, and communicate a strobe signal related to the data, at least one external terminal among the plurality of external terminals being configured to be capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: A semiconductor memory device and a data transmission system that operate in synchronization with a high speed system clock without using a synchronizing circuit such as a DLL or PLL. A semiconductor memory device that operates in synchronization with a system clock provided from outside, outputs a data strobe signal from a data strobe terminal when a read command is executed, and outputs read data in synchronization with the data strobe signal, is provided with a read preamble register that specifies the length of a read preamble outputted prior to output of the read data. A memory controller gives consideration to system clock frequency and internal delay time of the semiconductor memory device, and by optimally setting the read preamble length, can perform data transmission at high speed and without missing head data even if read data output start timing of the semiconductor memory device varies.

Abstract: A controller includes a set of first terminals to be coupled to a device that is under control of the controller, and a control circuit configured to generate and output onto the set of first terminals synchronous mode information including a selected one of selection and non-selection modes, the selection mode causing the device to return to the controller a first data signal while activating a first data strobe signal that is synchronous in phase with a system clock, the non-selection mode causing the device to return to the controller a second data signal while activating a second data strobe signal that is asynchronous in phase with the system clock signal, and edge specifying information including a selected one of first and second states, the first state causing the device to activate the first data strobe signal at a first timing.

Abstract: A semiconductor memory device operates in synchronization with a system clock, without using a synchronous circuit such as a DLL or a PLL. The semiconductor memory device includes a synchronous circuit for generating output signals phase aligned with the system clock, a synchronous circuit selection circuit that performs switching between a synchronous circuit selection mode and a synchronous circuit non-selection mode, and a reference edge specifying register that specifies an edge of an internal clock which serves as a reference for outputting read data in the synchronous circuit non-selection mode. In the synchronous circuit selection mode, the read data is output by adjusting a phase deviation of the internal clock with respect to the system clock, using the synchronous circuit. In the synchronous circuit non-selection mode, the read data is output in synchronization with the internal clock, without using the synchronous circuit.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: According to the system of the present invention, data (DQ) signals are outputted/received between a controller 100 and a memory 200 based on a data strobe signal sent out from the controller 100. The data strobe signal is independently and completely separated from a clock signal. The data strobe signal has a frequency different from a clock signal. Therefore, the memory 200 is not required to generate a read data strobe signal from the clock signal nor to send the read data strobe signal in synchronization with the clock signal.

Abstract: A semiconductor memory device and a data transmission system that operate in synchronization with a high speed system clock without using a synchronizing circuit such as a DLL or PLL. A semiconductor memory device that operates in synchronization with a system clock provided from outside, outputs a data strobe signal from a data strobe terminal when a read command is executed, and outputs read data in synchronization with the data strobe signal, is provided with a read preamble register that specifies the length of a read preamble outputted prior to output of the read data. A memory controller gives consideration to system clock frequency and internal delay time of the semiconductor memory device, and by optimally setting the read preamble length, can perform data transmission at high speed and without missing head data even if read data output start timing of the semiconductor memory device varies.