Patents by Inventor Atsuro Inada

Atsuro Inada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10267991
    Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: April 23, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Atsuro Inada
  • Patent number: 10078182
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 18, 2018
    Assignees: RENESAS ELECTRONICS CORPORATION, PHOTONICS ELECTRONICS TECHNOLOGY RESEARCH ASSOCIATION
    Inventors: Shinichi Watanuki, Akira Mitsuiki, Atsuro Inada, Tohru Mogami, Tsuyoshi Horikawa, Keizo Kinoshita
  • Patent number: 10038114
    Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: July 31, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Watanuki, Atsuro Inada
  • Publication number: 20180136391
    Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.
    Type: Application
    Filed: January 15, 2018
    Publication date: May 17, 2018
    Inventor: Atsuro INADA
  • Patent number: 9910219
    Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: March 6, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Atsuro Inada
  • Publication number: 20170263802
    Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.
    Type: Application
    Filed: May 26, 2017
    Publication date: September 14, 2017
    Inventors: Shinichi WATANUKI, Atsuro INADA
  • Patent number: 9696489
    Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.
    Type: Grant
    Filed: March 6, 2016
    Date of Patent: July 4, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Atsuro Inada
  • Patent number: 9634009
    Abstract: A fin-type field effect transistor (finFET) device includes a gate disposed over at least two fins, each fin defining a source outboard portion and a drain outboard portion extending beyond the gate. There is a source contact that electrically connects the source outboard portions of the fins, and similarly on the opposed side of the gate there is a drain contact electrically connecting the drain outboard portions of the fins. A first dielectric spacer layer is disposed adjacent to the gate and overlying the fins, and a second dielectric spacer layer is disposed adjacent to the first spacer layer and also overlying the fins. The second dielectric spacer layer electrically isolates the gate from the drain contact and/or from the source contact. A method of making a finFET device is also detailed.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Atsuro Inada, Sivananda K. Kanakasabapathy
  • Publication number: 20170068051
    Abstract: When an optical waveguide is formed, an area of an opening of a resist mask is equal to an area of a semiconductor layer for a dummy pattern exposed from the resist mask, and the semiconductor layer for the dummy pattern exposed from the resist mask has a uniform thickness in a region in which the dummy pattern is formed. As a result, an effective pattern density does not change in etching the semiconductor layer for the dummy pattern, and accordingly, it is possible to form a rib-shaped optical waveguide having desired dimensions and a desired shape.
    Type: Application
    Filed: August 22, 2016
    Publication date: March 9, 2017
    Inventors: Shinichi WATANUKI, Akira MITSUIKl, Atsuro INADA, Tohru MOGAMI, Tsuyoshi HORIKAWA, Keizo KINOSHITA
  • Publication number: 20170038530
    Abstract: First, half etching is performed to a semiconductor layer formed on an insulating layer to form trenches at positions of slab-portion regions in which slab portions are to be formed. After filling the trenches with an insulating film, a resist mask which covers the semiconductor layer at a projecting-portion region in which a projecting portion is to be formed and whose pattern ends are located on upper surfaces of the insulating films is formed on upper surfaces of the semiconductor layer and the insulating film, and full etching is performed to the semiconductor layer with using the resist mask and the insulating film as an etching mask, thereby forming an optical waveguide constituted of the projecting portion and the slab portions. Thereafter, a first interlayer insulating film is formed to cover the optical waveguide.
    Type: Application
    Filed: July 15, 2016
    Publication date: February 9, 2017
    Inventor: Atsuro INADA
  • Publication number: 20160282554
    Abstract: A semiconductor substrate, an insulating layer made of silicon oxide formed on the semiconductor substrate and a semiconductor layer made of silicon formed on the insulating layer are provided, and the semiconductor layer constitutes an optical waveguide in an optical signal transmission line section and an optical modulator in an optical modulation section. Also, the insulating layer is removed except for a part thereof to have a hollow structure with a cavity, and both side surfaces and a lower surface of each of the semiconductor layers constituting the optical waveguide and the optical modulator are exposed and covered with air.
    Type: Application
    Filed: March 6, 2016
    Publication date: September 29, 2016
    Inventors: Shinichi WATANUKI, Atsuro INADA
  • Publication number: 20140162447
    Abstract: A method for fabricating a field effect transistor device includes patterning a fin on substrate, patterning a gate stack over a portion of the fin and a portion of an insulator layer arranged on the substrate, forming a protective barrier over the gate stack, a portion of the fin and a portion of the insulator layer, the protective barrier enveloping the gate stack, depositing a second insulator layer over portions of the fin and the protective barrier, performing a first etching process to selectively remove portions of the second insulator layer to define cavities that expose portions of source and drain regions of the fin without appreciably removing the protective barrier, and depositing a conductive material in the cavities.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Lisa F. Edge, Martin M. Frank, Balasubramanian S. Haran, Atsuro Inada, Sivananda K. Kanakasabapathy, Andreas Knorr, Vijay Narayanan, Vamsi K. Paruchuri, Soon-cheon Seo
  • Patent number: 8492227
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 23, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Patent number: 8123901
    Abstract: The wafer processing apparatus 100 included in an etching apparatus selectively etches the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 as a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying therethgouh a process gas etching the peripheral portion, an etching-interfering gas introducing duct 118 supplying therethrough an etching-interfering gas interfering supply of the process gas to the center portion of the wafer, and a movable alignment mechanism 102 aligning the wafer on the lower electrode 112. The etching-interfering gas introducing duct 118 and the process gas introducing duct 120 can be provided in an upper electrode 106.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 28, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Atsuro Inada, Kazuhiko Ueno
  • Publication number: 20110053367
    Abstract: An etching stopper film is formed over a first insulating film. Then, a second insulating film is formed with a thickness that allows concave and convex portions formed due to a first gate electrode to remain. Then, anisotropic etching is performed using the etching stopper film as a stopper to remove the second insulating film over a second gate electrode and form a first side wall spacer of the first gate electrode. Then, the etching stopper film is removed. Then, anisotropic etching is performed on the first insulating film to form a second side wall spacer over the second gate electrode and form a third side wall spacer which is disposed inside the first side wall spacer over the first gate electrode.
    Type: Application
    Filed: July 16, 2010
    Publication date: March 3, 2011
    Inventors: Akira MITSUIKI, Atsuro Inada
  • Publication number: 20080194107
    Abstract: The present invention aims to improve the controllability of dimensions at the time when a silicon substrate or a film formed on top of the silicon substrate is etched. For this purpose, a SiN film is formed so as to be in contact with the top of an element-forming surface of a silicon substrate, and the SiN film is selectively removed to form an opening portion. Then, a plasma processing is carried out on the element-forming surface of the silicon substrate to remove deposits attached on sidewalls of the opening portion formed in the SiN film. After that, the silicon substrate is selectively removed by using the SiN film as a mask to form a concave portion in the silicon substrate.
    Type: Application
    Filed: February 5, 2008
    Publication date: August 14, 2008
    Applicant: NEC Electronics Corporation
    Inventors: Akira Mitsuiki, Atsuro Inada
  • Publication number: 20060086462
    Abstract: The wafer processing apparatus 100 included in an etching apparatus selectively etches the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 as a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying therethgouh a process gas etching the peripheral portion, an etching-interfering gas introducing duct 118 supplying therethrough an etching-interfering gas interfering supply of the process gas to the center portion of the wafer, and a movable alignment mechanism 102 aligning the wafer on the lower electrode 112. The etching-interfering gas introducing duct 118 and the process gas introducing duct 120 can be provided in an upper electrode 106.
    Type: Application
    Filed: October 20, 2005
    Publication date: April 27, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Atsuro Inada, Kazuhiko Ueno
  • Publication number: 20060086461
    Abstract: A wafer processing apparatus 100 involved in an etching apparatus takes part in selective etching of the peripheral portion of a wafer 200. The wafer processing apparatus 100 includes a lower electrode 112 which is a stage on which the wafer 200 is placed, a process gas introducing duct 120 supplying a process gas etching the peripheral portion, and a plurality of etching-interfering gas introducing ducts 118a, 118b, 118c and 118d supplying etching-interfering gas an interfering supply of the process gas to the center of the wafer 200. The etching-interfering gas coming through the plurality of etching-interfering gas introducing ducts 118a to 118d is supplied in a plurality of directions, while being independently controlled in each supply volume.
    Type: Application
    Filed: October 19, 2005
    Publication date: April 27, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Atsuro Inada, Kazuhiko Ueno