Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: An object is to provide a Ro-scull which can suppress a decrease in thrust force by water resistance generated during turn-over operation and can realize high-speed cruise of a boat. The Ro-scull has a Ro-arm 1 and a Ro-blade 2 having a flat part 12 perpendicular to the Ro-arm 1. The Ro-arm 1 is attached to an upper end portion of the Ro-blade 2 from an obliquely lower side. Namely, the Ro-arm 1 and the Ro-blade 2 are joined to each other while the Ro-arm 1 “receives” the Ro-blade 2. A Ro-handle 3 is arranged not on the upper surface side but on the lower surface side of the Ro-arm 1.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: An object is to provide a Ro-scull which can suppress a decrease in thrust force by water resistance generated during turn-over operation and can realize high-speed cruise of a boat. The Ro-scull has a Ro-arm 1 and a Ro-blade 2 having a flat part 12 perpendicular to the Ro-arm 1. The Ro-arm 1 is attached to an upper end portion of the Ro-blade 2 from an obliquely lower side. Namely, the Ro-arm 1 and the Ro-blade 2 are joined to each other while the Ro-arm 1 “receives” the Ro-blade 2. A Ro-handle 3 is arranged not on the upper surface side but on the lower surface side of the Ro-arm 1.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

Abstract: Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Abstract: According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.

Abstract: The invention relates to a filter device, and is intended to prevent drastic changes of output modulation signal and assures the performance as modulator if output modulation signal is transmitted and stopped frequency by using TDMA in communication control. To achieve the object, the invention comprises a shift register 1, a plurality of memories 2 connected to this shift register 1 and increased in the bit width of input address by one bit each, and a selector 3 for selecting outputs from these plurality of memories 2, in which the output of the shift register 1 is used as a higher side address of each one of the memories 2, a lower side address of each one of the memory addresses is common, the bit width of the higher side address increases by one bit each starting from one bit, and addresses are assigned sequentially from the lower side of the higher side address of the memories 2 depending on the shift from the lowest side bit of the shift register 1.