Patents by Inventor Atsushi Hieno
Atsushi Hieno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11152334Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.Type: GrantFiled: September 5, 2019Date of Patent: October 19, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yusuke Tanaka, Atsushi Hieno, Tsutomu Nakanishi, Yasuhito Yoshimizu, Masayoshi Tagami
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Publication number: 20200294971Abstract: In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.Type: ApplicationFiled: September 5, 2019Publication date: September 17, 2020Applicant: Toshiba Memory CorporationInventors: Yusuke TANAKA, Atsushi Hieno, Tsutomu Nakanishi, Yasuhito Yoshimizu, Masayoshi Tagami
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Patent number: 10249531Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.Type: GrantFiled: February 9, 2018Date of Patent: April 2, 2019Assignee: Toshiba Memory CorporationInventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
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Publication number: 20190088539Abstract: A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.Type: ApplicationFiled: February 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Atsushi Hieno, Tsutomu Nakanishi, Yusuke Tanaka, Yasuhito Yoshimizu, Akihiko Happoya
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Publication number: 20190088872Abstract: A storage device according to an embodiment includes a first conductive layer, a second conductive layer, and a resistance change layer. The resistance change layer is positioned between the first conductive layer and the second conductive layer. The resistance change layer including an organic compound. The organic compound has at least one first functional group selected from the group consisting of an amino group, a thiol group, a carboxy group, and an azide group, and the organic compound has one or less aromatic rings.Type: ApplicationFiled: February 9, 2018Publication date: March 21, 2019Applicant: Toshiba Memory CorporationInventors: Yusuke Tanaka, Atsushi Hieno
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Patent number: 10147612Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.Type: GrantFiled: August 28, 2017Date of Patent: December 4, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Nakanishi, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
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Publication number: 20180277390Abstract: A metal pattern forming method according to an embodiment includes forming a metal film on a surface of a substrate by an electroless plating method, the substrate including a first layer including a protrusion and a recess, and a film thickness of the metal film being a half or more of a width of the recess; and performing wet etching, the metal film in the recess removed by the wet etching and the metal film on the protrusion remained after the wet etching.Type: ApplicationFiled: August 28, 2017Publication date: September 27, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Tsutomu NAKANISHI, Yusuke Tanaka, Atsushi Hieno, Yasuhito Yoshimizu, Akihiko Happoya
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Publication number: 20180274102Abstract: A method of forming a metal pattern includes forming a catalyst adsorption layer by bringing a surface of a substrate into contact with a solution, the substrate having a base region and a plurality of protrusions provided on the base region, the base region includes a first material, the protrusions includes a second material different from the first material, the first and the second material being exposed on the surface, and the solution containing a compound having a triazine skeleton, a first functional group of any one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, and an azido group, forming a catalyst layer on the catalyst adsorption layer, forming a metal film on the catalyst layer by an electroless plating method, and removing the metal film on the protrusions.Type: ApplicationFiled: September 7, 2017Publication date: September 27, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Yusuke TANAKA, Atsushi HIENO, Tsutomu NAKANISHI, Yasuhito YOSHIMIZU, Akihiko HAPPOYA
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Patent number: 9659816Abstract: A pattern forming method in an embodiment includes forming, on or above a substrate, a block copolymer layer containing a first polymer and a second polymer having lower surface energy than the first polymer, heat treating the block copolymer layer to separate the block copolymer layer into a first phase containing the first polymer and a second phase containing the second polymer, and using an atomic layer deposition process, selectively forming a metal layer on the first phase and selectively removing the second phase.Type: GrantFiled: March 9, 2016Date of Patent: May 23, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Hieno, Koji Asakawa
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Patent number: 9608203Abstract: A method for manufacturing a memory device of an embodiment includes: forming on a substrate a block copolymer layer which contains a first polymer and a second polymer having lower surface energy than that of the first polymer; performing thermal treatment on the block copolymer layer, to separate the block copolymer layer such that a first phase containing the first polymer and extending in the first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed; selectively forming on the first phase a first metal wiring layer extending in the first direction; forming on the first metal wiring layer a memory layer where resistance changes by application of a voltage; and forming on the memory layer a second metal wiring layer which extends in a second direction intersecting in the first direction.Type: GrantFiled: September 1, 2015Date of Patent: March 28, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Hieno, Koji Asakawa
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Publication number: 20160284560Abstract: A pattern forming method in an embodiment includes forming, on or above a substrate, a block copolymer layer containing a first polymer and a second polymer having lower surface energy than the first polymer, heat treating the block copolymer layer to separate the block copolymer layer into a first phase containing the first polymer and a second phase containing the second polymer, and using an atomic layer deposition process, selectively forming a metal layer on the first phase and selectively removing the second phase.Type: ApplicationFiled: March 9, 2016Publication date: September 29, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi HIENO, Koji Asakawa
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Publication number: 20160087206Abstract: A method for manufacturing a memory device of an embodiment includes: forming on a substrate a block copolymer layer which contains a first polymer and a second polymer having lower surface energy than that of the first polymer; performing thermal treatment on the block copolymer layer, to separate the block copolymer layer such that a first phase containing the first polymer and extending in the first direction and a second phase containing the second polymer and extending in the first direction are alternately arrayed; selectively forming on the first phase a first metal wiring layer extending in the first direction; forming on the first metal wiring layer a memory layer where resistance changes by application of a voltage; and forming on the memory layer a second metal wiring layer which extends in a second direction intersecting in the first direction.Type: ApplicationFiled: September 1, 2015Publication date: March 24, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi HIENO, Koji ASAKAWA
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Patent number: 9291908Abstract: According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.Type: GrantFiled: June 1, 2015Date of Patent: March 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Hieno, Shigeki Hattori, Hiroko Nakamura, Satoshi Mikoshiba, Koji Asakawa, Masahiro Kanno, Yuriko Seino, Tsukasa Azuma
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Patent number: 9177818Abstract: According to one embodiment, a pattern formation method includes: forming a block copolymer layer containing a polystyrene derivative and an acrylic having 6 or more carbon atoms on a side chain in an opening of a resist layer provided on an underlayer and having the opening; forming a first layer containing the polystyrene derivative and a second layer containing the acrylic in the opening by phase-separating the block copolymer layer; and removing the second layer.Type: GrantFiled: October 29, 2013Date of Patent: November 3, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Atsushi Hieno, Hiroko Nakamura, Koji Asakawa
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Publication number: 20150261092Abstract: According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.Type: ApplicationFiled: June 1, 2015Publication date: September 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi HIENO, Shigeki HATTORI, Hiroko NAKAMURA, Satoshi MlKOSHIBA, Koji ASAKAWA, Masahiro KANNO, Yuriko SEINO, Tsukasa AZUMA
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Patent number: 9073284Abstract: According to one embodiment, there is provided a method of forming a pattern, including forming a thermally crosslinkable molecule layer including a thermally crosslinkable molecule on a substrate, forming a photosensitive composition layer including a photosensitive composition on the thermally crosslinkable molecule layer, chemically binding the thermally crosslinkable molecule to the photosensitive composition by heating, selectively irradiating the photosensitive composition layer with energy rays, forming a block copolymer layer including a block copolymer on the photosensitive composition layer, and forming a microphase-separated structure in the block copolymer layer.Type: GrantFiled: September 25, 2012Date of Patent: July 7, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Atsushi Hieno, Shigeki Hattori, Hiroko Nakamura, Satoshi Mikoshiba, Koji Asakawa, Masahiro Kanno, Yuriko Seino, Tsukasa Azuma
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Patent number: 9017930Abstract: According to one embodiment, a pattern formation method includes forming a pattern on a layer. The layer has a first surface energy and includes a silicon compound. The pattern has a second surface energy different from the first surface energy. The method includes forming a block polymer on the layer and the pattern. The method includes forming a structure selected from a lamellar structure and a cylindrical structure of the block polymer containing polymers arranged by microphase separation. The lamellar structure is oriented perpendicularly to the layer surface. The cylindrical structure is oriented so as to have an axis parallel to a normal line of the layer surface. The second surface energy is not less than a maximum value of surface energies of the polymers or not more than a minimum value of the surface energies of the polymers.Type: GrantFiled: September 20, 2012Date of Patent: April 28, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Hiroko Nakamura, Satoshi Mikoshiba, Atsushi Hieno, Shigeki Hattori
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Patent number: 8808973Abstract: According to one embodiment, there is provided a method of forming a pattern including forming a polymer layer on a substrate, the polymer layer including a first and second regions, selectively irradiating either of the first and second regions with energy rays or irradiating the first and second regions with energy rays under different conditions to cause a difference in surface free energy between the first and second regions, thereafter, forming a block copolymer layer on the polymer layer, and causing microphase separation in the block copolymer layer to simultaneously form first and second microphase-separated structures on the first and second regions, respectively.Type: GrantFiled: February 22, 2012Date of Patent: August 19, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Mikoshiba, Koji Asakawa, Hiroko Nakamura, Shigeki Hattori, Atsushi Hieno, Tsukasa Azuma, Yuriko Seino, Masahiro Kanno
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Publication number: 20140127910Abstract: According to one embodiment, a pattern formation method includes: forming a block copolymer layer containing a polystyrene derivative and an acrylic having 6 or more carbon atoms on a side chain in an opening of a resist layer provided on an underlayer and having the opening; forming a first layer containing the polystyrene derivative and a second layer containing the acrylic in the opening by phase-separating the block copolymer layer; and removing the second layer.Type: ApplicationFiled: October 29, 2013Publication date: May 8, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Atsushi HIENO, Hiroko Nakamura, Koji Asakawa
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Patent number: 8636914Abstract: According to one embodiment, there is provided a method of forming a pattern, includes forming a guide pattern including a first region having a first surface energy and a second region having a second surface energy on a to-be-processed film, the first and second regions alternately arranged in one direction, forming a block copolymer layer on the guide pattern, and causing microphase separation in the block copolymer layer, the microphase-separated structure is a lamellar block copolymer pattern.Type: GrantFiled: March 27, 2012Date of Patent: January 28, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroko Nakamura, Satoshi Tanaka, Satoshi Mikoshiba, Atsushi Hieno, Shigeki Hattori