Patents by Inventor Atsushi Hiraishi

Atsushi Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11183693
    Abstract: One aspect provides a resin composition that is used for an electrode of a power storage device and that has excellent ion permeability while ensuring good binding properties with an electrode. One aspect of the present disclosure relates to a resin composition for an electrode of a power storage device. The resin composition contains polymer particles. The polymer particles have ion permeability. A rate of change in elasticity of the polymer particles before and after treatment with an electrolyte solution [(modulus of elasticity after treatment)/(modulus of elasticity before treatment)] is 30% or less.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: November 23, 2021
    Assignee: KAO CORPORATION
    Inventors: Atsushi Hiraishi, Kazuo Kuwahara, Kei Takahashi, Kazuo Oki, Hideki Goto
  • Publication number: 20210188642
    Abstract: A method for producing a semiconducting SWCNT dispersion of the present invention comprises: a step A of preparing a to-be-separated SWCNT dispersion that includes a SWCNT mixture, an aqueous medium, and a polymer including a structural unit A derived from a monomer represented by Formula (1), and a step B of centrifuging the to-be-separated SWCNT dispersion and subsequently collecting a supernatant including the semiconducting SWCNT from the centrifuged to-be-separated SWCNT dispersion. The weight-average molecular weight of the polymer is 1,000 or more and 100,000 or less.
    Type: Application
    Filed: May 22, 2019
    Publication date: June 24, 2021
    Applicant: KAO CORPORATION
    Inventor: Atsushi HIRAISHI
  • Publication number: 20200381734
    Abstract: One aspect provides a resin composition that is used for an electrode of a power storage device and that has excellent ion permeability while ensuring good binding properties with an electrode. One aspect of the present disclosure relates to a resin composition for an electrode of a power storage device. The resin composition contains polymer particles. The polymer particles have ion permeability. A rate of change in elasticity of the polymer particles before and after treatment with an electrolyte solution [(modulus of elasticity after treatment)/(modulus of elasticity before treatment)] is 30% or less.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 3, 2020
    Applicant: Kao Corporation
    Inventors: Atsushi HIRAISHI, Kazuo KUWAHARA, Kei TAKAHASHI, Kazuo OKI, Hideki GOTO
  • Publication number: 20200313192
    Abstract: A negative electrode constituting a non-aqueous electrolyte secondary battery, which is an example of an embodiment, comprises a negative-electrode mixture layer including a negative-electrode active material and a binder agent. The negative electrode includes, as the binder agent, at least a polymer constituted by a constituent unit A represented by formula (1), a constituent unit B represented by formula (2), and a constituent unit C represented by formula (3). The molar ratio (l/m) of the constituent unit A to the constituent unit B is from 0.2 to 1.8.
    Type: Application
    Filed: December 7, 2018
    Publication date: October 1, 2020
    Applicants: Panasonic Corporation, Kao Corporation
    Inventors: Naoyuki Wada, Atsushi Hiraishi, Kei Takahashi
  • Patent number: 10720201
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal: a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: July 21, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Atsushi Hiraishi
  • Publication number: 20190371388
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal: a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: Micron Technology, Inc.
    Inventor: Atsushi Hiraishi
  • Patent number: 10410712
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 10, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Atsushi Hiraishi
  • Publication number: 20180277194
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.
    Type: Application
    Filed: May 7, 2018
    Publication date: September 27, 2018
    Applicant: Micron Technology, Inc.
    Inventor: Atsushi Hiraishi
  • Patent number: 10049722
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: August 14, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Publication number: 20180197595
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Application
    Filed: September 28, 2017
    Publication date: July 12, 2018
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Patent number: 9984740
    Abstract: Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes a signal receiver that receives information signal; a control circuit that provides a plurality of control signals; and a signal receiver replica circuit that receives a first reference signal. The signal receiver replica circuit includes a plurality of receivers. Each receiver of the plurality of receivers receives the first reference signal and a corresponding control signal of the plurality of control signals, and further provides an output signal.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: May 29, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Atsushi Hiraishi
  • Patent number: 9837137
    Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: December 5, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Patent number: 9805786
    Abstract: Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: October 31, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi, Atsuo Koshizuka
  • Patent number: 9570375
    Abstract: Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: February 14, 2017
    Assignee: Longitude Semiconductor S.a.r.l.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Yasuhiro Takai
  • Publication number: 20160267962
    Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
    Type: Application
    Filed: May 19, 2016
    Publication date: September 15, 2016
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Patent number: 9368185
    Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: June 14, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Patent number: 9076500
    Abstract: Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: July 7, 2015
    Assignee: PS4 LUXCO S.A.R.L.
    Inventors: Fumiyuki Osanai, Toshio Sugano, Atsushi Hiraishi
  • Publication number: 20150098289
    Abstract: A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.
    Type: Application
    Filed: October 7, 2014
    Publication date: April 9, 2015
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Patent number: 8988952
    Abstract: Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: March 24, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Seiji Narui, Yasuhiro Takai
  • Patent number: 8922029
    Abstract: An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TL0 from the data transferring element to a first branch point S1 where a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TL1 from the first branch point S1 to a second branch point S2 where a second branch line is branched. A wiring length TL3 from the second branch point S2 to a third branch point S3 where a third branch line is branched is configured to become greater than the wiring lengths TL0 and TL1.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 30, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Atsushi Hiraishi, Toshio Sugano, Masahiro Yamaguchi, Yoji Nishio, Tsutomu Hara, Koichiro Aoki