Patents by Inventor Atsushi Hiraishi

Atsushi Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090001548
    Abstract: A semiconductor package which includes: a semiconductor chip which includes a signal terminal for inputting and outputting electrical signals and a ground terminal; and a package substrate which includes a semiconductor chip mounting surface on which the semiconductor chip is mounted, and a terminal electrode forming surface on which a signal terminal electrode electrically connected to the signal terminal and a ground terminal electrode electrically connected to the ground terminal are arranged in an array pattern, wherein: on the semiconductor chip mounting surface, there is provided a first signal wiring connected to the signal terminal, a ground wiring connected to the ground terminal, and a ground conductive layer connected to the ground wiring and is provided in a planar pattern in an area excluding the forming area of the first signal wiring; on the terminal electrode forming surface, there is provided a second signal wiring connected to the signal terminal electrode, and a ground fine wiring connected
    Type: Application
    Filed: June 20, 2008
    Publication date: January 1, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Fumiyuki Osanai, Toshio Sugano, Atsushi Hiraishi
  • Patent number: 7440289
    Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.
    Type: Grant
    Filed: November 27, 2007
    Date of Patent: October 21, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Toshio Sugano, Shunichi Saito, Atsushi Hiraishi
  • Publication number: 20080203584
    Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
    Type: Application
    Filed: April 14, 2008
    Publication date: August 28, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Mitsuaki Katagiri, Atsushi Hiraishi, Fumiyuki Osanai
  • Publication number: 20080164058
    Abstract: A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring are arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.
    Type: Application
    Filed: December 20, 2007
    Publication date: July 10, 2008
    Inventors: Shunichi Saito, Toshio Sugano, Atsushi Hiraishi
  • Publication number: 20080123303
    Abstract: A memory module includes a memory chip MC1 disposed at a position opposite to a memory buffer via a module substrate, a memory chip MC3 disposed at a position not opposite to the memory buffer via the module substrate, and a memory chip MC11 disposed at a position opposite to the memory chip MC3 via the module substrate. A branch point at which a wiring part connected to the memory chip MC1 and a wiring part connected to the memory chips MC3 and MC11 are branched is positioned at the memory buffer side from the viewpoint of the intermediate point between the planar mounting position of the memory buffer and the planar mounting position of the memory chips MC3 and MC11. Accordingly, the wiring length of the wiring part can be made sufficiently short.
    Type: Application
    Filed: November 27, 2007
    Publication date: May 29, 2008
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Toshio Sugano, Shunichi Saito, Atsushi Hiraishi
  • Patent number: 7375422
    Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: May 20, 2008
    Assignee: Elpida Memory, Inc.
    Inventors: Mitsuaki Katagiri, Atsushi Hiraishi, Fumiyuki Osanai
  • Publication number: 20070273021
    Abstract: A semiconductor package comprises a substrate, which has two surfaces and comprises first and second electrical paths. On one of the surfaces, a semiconductor chip is mounted. The semiconductor chip comprises a plurality of pads, which include a first pad to be supplied with a power supply and a second pad to be grounded. On the other surface, at least one bypass capacitor is mounted. The bypass capacitor comprises first and second terminals, which are connected to the first and the second pads through the first and the second electrical paths, respectively.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 29, 2007
    Inventors: Fumiyuki Osanai, Atsushi Hiraishi, Toshio Sugano, Tsuyoshi Tomoyama, Satoshi Isa, Masahiro Yamaguchi, Masanori Shibamoto
  • Publication number: 20070213428
    Abstract: A water dispersion for inkjet printing which includes water-insoluble polymer particles. The water-insoluble polymer particles contain silica particles and a pigment other than the silica particles. A water-based ink containing the water dispersion is excellent in the storage stability and effectively reduces the bronze phenomenon of printed images.
    Type: Application
    Filed: March 7, 2007
    Publication date: September 13, 2007
    Inventors: Atsushi Hiraishi, Takehiro Tsutsumi
  • Publication number: 20060137844
    Abstract: The powder composition for paper manufacturing of the invention contains a hydrophobic organic compound (A), an emulsifying and dispersing agent (B), and optionally water-soluble saccharides (C) added based on necessity and has an average particle diameter of 0.1 to 2,000 ?m.
    Type: Application
    Filed: July 29, 2004
    Publication date: June 29, 2006
    Inventors: Yoshihito Hamada, Kazuo Kubota, Atsushi Hiraishi, Jun Kozuka, Takahiro Kawaguchi, Tsutomu Miyahara, Hiroshi Noro, Koichi Ohori, Haruyuki Sato
  • Publication number: 20060118937
    Abstract: Corresponding parts to a first path portion in a first signal transmission path to a first semiconductor chip are an interconnection member and a second path portion a second signal transmission path to a second semiconductor chip and are not formed on the first tape. An electric length of the second signal transmission path is allowed to be adjusted independently of the first tape, so that the electric length of the second signal transmission path can be easily made equal to or substantially equal to that of the first signal transmission path.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 8, 2006
    Inventors: Mitsuaki Katagiri, Atsushi Hiraishi, Fumiyuki Osanai
  • Patent number: 6271687
    Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
    Type: Grant
    Filed: March 21, 2000
    Date of Patent: August 7, 2001
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
  • Patent number: 6046609
    Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: April 4, 2000
    Assignees: Hitachi, Ltd., Hitachi ULSI Engineering Corp.
    Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
  • Patent number: 5963483
    Abstract: A synchronous memory unit which includes a plurality of input buffers for receiving address data, a plurality of input latches for holding and outputting address data from in the input buffers according to a clock signal, a plurality of decoders for decoding the address data from the input latches, and a memory cell array having a plurality of memory cells which store and output data signals via bit lines according to the address data decoded by the decoders. Also provided are a sense amplifier for amplifying the output data signals on the bit lines, a selector for selecting one of the amplified output data signals according to the address data decoded by the decoders, and a selector output latch for holding and outputting the amplified output data signal from the selector according to the clock signal. An output latch holds and outputs the amplified output data signal from the selector output latch according to the clock signal.
    Type: Grant
    Filed: August 14, 1998
    Date of Patent: October 5, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Hideharu Yahata, Kenichi Fukui, Yoji Nishio, Atsushi Hiraishi, Sadayuki Morita
  • Patent number: 5854562
    Abstract: A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.
    Type: Grant
    Filed: April 15, 1997
    Date of Patent: December 29, 1998
    Assignees: Hitachi, Ltd, Hitachi ULSI Engineering Corp.
    Inventors: Hiroshi Toyoshima, Masashige Harada, Tomohiro Nagano, Yoji Nishio, Atsushi Hiraishi, Kunihiro Komiyaji, Hideharu Yahata, Kenichi Fukui, Hirofumi Zushi, Takahiro Sonoda, Haruko Kawachino, Sadayuki Morita
  • Patent number: 5834851
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5787043
    Abstract: A semiconductor device is provided which comprises a memory mat formed by dividing a memory into a plurality of blocks and a circuit arrangement disposed at every memory mat block for generating access suppression signals at least for defective memory cells within that block. Using this arrangement, the access speed to a redundant memory cell array for relieving the defects is increased so that a semiconductor memory device capable of a high speed operation is obtained.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: July 28, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Yuji Yokoyama, Atsushi Hiraishi, Masahiro Iwamura, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Koichi Motohashi
  • Patent number: 5767554
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: June 16, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5731219
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising an SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs, and a method of forming this device. The gate electrodes of the drive MISFETs and of the transfer MISFETs of the memory cell, and the word lines, are individually formed of different conductive layers. The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The source line is formed of a conductive layer identical to that of the word line. An oxidation resisting film is formed on the gate electrodes of the drive MISFETs so as to reduce stress caused by oxidization of edge portions of these gate electrodes, and to reduce a resulting leakage current.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: March 24, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5726488
    Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: March 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Yoshiaki Yazawa, Atsushi Hiraishi, Masataka Minami, Takahiro Nagano, Takahide Ikeda, Naohiro Momma
  • Patent number: 5700704
    Abstract: A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: December 23, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake