Patents by Inventor Atsushi Hiraishi

Atsushi Hiraishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5680066
    Abstract: A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitu
    Type: Grant
    Filed: January 13, 1994
    Date of Patent: October 21, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira Ide, Masahiro Yamamura, Hideaki Uchida
  • Patent number: 5675548
    Abstract: An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuit which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
    Type: Grant
    Filed: February 29, 1996
    Date of Patent: October 7, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yokoyama, Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Nobuyuki Gotou, Akira Ide
  • Patent number: 5656836
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected-with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 12, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5652457
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.
    Type: Grant
    Filed: November 30, 1994
    Date of Patent: July 29, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5619151
    Abstract: A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; a
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: April 8, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yuji Yokoyama, Nozomu Matsuzaki, Tatsumi Yamauchi, Yutaka Kobayashi, Nobuyuki Gotou, Akira ide, Masahiro Yamamura, Hideaki Uchida
  • Patent number: 5572480
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: November 5, 1996
    Assignee: Hitachi Ltd.
    Inventors: Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake
  • Patent number: 5544125
    Abstract: An arrangement which is particularly effective for decoders in semiconductor memory circuits which use, for example, common NMOS to receive one input for a plurality of logic decoder gates is provided includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, and each being coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. An improved read/write arrangement is also provided for such semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation. This enhances the writing speed by removing the load of the common read line during writing.
    Type: Grant
    Filed: February 6, 1995
    Date of Patent: August 6, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yokoyama, Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Nobuyuki Gotou, Akira Ide
  • Patent number: 5512497
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: July 8, 1994
    Date of Patent: April 30, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
  • Patent number: 5502820
    Abstract: An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
    Type: Grant
    Filed: February 8, 1995
    Date of Patent: March 26, 1996
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraishi, Takashi Akioka, Yutaka Kobayashi, Yuji Yokoyama, Masahiro Iwamura, Tatsumi Yamauchi, Shigeru Takahashi, Hideaki Uchida, Akira Ide
  • Patent number: 5398318
    Abstract: An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: March 14, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Atsushi Hiraishi, Takashi Akioka, Yutaka Kobayashi, Yuji Yokoyama, Masahiro Iwamura, Tatsumi Yamauchi, Shigeru Takahashi, Hideaki Uchida, Akira Ide
  • Patent number: 5387827
    Abstract: A semiconductor integrated logic circuit is provided which includes a plurality of logic gates each having a first input terminal for respectively receiving first input signals, wherein each of the logic gates is coupled to a common node. In one embodiment, first and second switching elements are also coupled to the common node. The first and second switching elements are both coupled to a second input terminal for receiving a second input signal which is common to the plurality of logic gates, and both operate complementary to one another in response to the second input signal. This arrangement is particularly effective for decoders in semiconductor memory circuits which use a common NMOS to receive one input for a plurality of logic decoder gates. An improved read/write arrangement is also provided for semiconductor memory circuits which includes circuitry to prevent connection of a common read line to the data lines during the writing operation.
    Type: Grant
    Filed: January 22, 1991
    Date of Patent: February 7, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Yuji Yokoyama, Takashi Akioka, Masahiro Iwamura, Atsushi Hiraishi, Yutaka Kobayashi, Tatsumi Yamauchi, Shigeru Takahashi, Nobuyuki Gotou, Akira Ide
  • Patent number: 5354699
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: October 22, 1992
    Date of Patent: October 11, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
  • Patent number: 5274594
    Abstract: A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.
    Type: Grant
    Filed: February 25, 1992
    Date of Patent: December 28, 1993
    Assignee: Hitachi, Ltd.
    Inventors: Kazumasa Yanagisawa, Atsushi Hiraishi, Hideyuki Aoki, Satoshi Oguchi, Sadayuki Ohkuma
  • Patent number: 5057894
    Abstract: Disclosed is a bipolar-CMOS LSI manufactured by a simplified process and realizing a higher density of integration as well as a higher operating speed, in which a base lead-out electrode of a bipolar transistor and respective gate electrodes of a p-channel MISFET and an n-channel MISFET of CMOS transistors are made of an identical conductor film, and the conductor film of the gate electrode of the p-channel MISFET is of p-type, while that of the gate electrode of the n-channel MISFET is of n-type.
    Type: Grant
    Filed: May 23, 1990
    Date of Patent: October 15, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Takahide Ikeda, Kouichirou Yamada, Osamu Saito, Masanori Odaka, Nobuo Tamba, Katsumi Ogiue, Atsushi Hiraishi, Atsuo Watanabe, Mitsuru Hirao, Akira Fukami, Masayuki Ohayashi, Tadashi Kuramoto
  • Patent number: 5029323
    Abstract: A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
    Type: Grant
    Filed: August 29, 1989
    Date of Patent: July 2, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Nobuo Tanba, Nobuyuki Gotoo, Kazunori Onozawa, Atsushi Hiraishi
  • Patent number: 4984200
    Abstract: Herein disclosed is a semiconductor integrated circuit device comprising a SRAM which is composed of a memory cell having its high resistance load element and power source voltage line connected with the information storage node of a flip-flop circuit through a conductive layer. At the same fabrication step as that of forming the plate electrode layer of a capacity element over the conductive layer formed on the portion of the information storage node through a dielectric film, an electric field shielding film for shielding the field effect of a data line is formed over the high resistance load element through an inter-layer insulation film.
    Type: Grant
    Filed: November 15, 1988
    Date of Patent: January 8, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Ryuichi Saitoo, Osamu Saitoo, Takahide Ikeda, Mitsuru Hirao, Atsushi Hiraishi
  • Patent number: 4963973
    Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: October 16, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Yoshiaki Yazawa, Atsushi Hiraishi, Masataka Minami, Takahiro Nagano, Takahide Ikeda, Naohiro Momma
  • Patent number: 4916500
    Abstract: The present invention relates to a semiconductor device comprising a semiconductor substrate of a first conductivity type or an insulator, a source comprising an impurity layer of a second conductivity type disposed on said semiconductor substrate or said insulator, a drain comprising an impurity layer of the second conductivity type disposed on said semiconductor substrate or said insulator, an impurity layer of the first conductivity type formed between said source and said drain, a gate formed on said impurity layer of the first conductivity type via an insulation film, and an impurity layer of the second conductivity type having an impurity concentration lower than that of said source and said drain, said impurity layer of the second conductivity type being disposed between said source, said drain and said impurity layer of the first conductivity type, and said semiconductor substrate of the first conductivity type or said insulator.
    Type: Grant
    Filed: July 29, 1987
    Date of Patent: April 10, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Yazawa, Atsuo Watanabe, Atsushi Hiraishi, Masataka Minami, Takahiro Nagano
  • Patent number: 4868626
    Abstract: A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
    Type: Grant
    Filed: April 30, 1987
    Date of Patent: September 19, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Nobuo Tanba, Nobuyuki Gotoo, Kazunori Onozawa, Atsushi Hiraishi
  • Patent number: 4672416
    Abstract: A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.
    Type: Grant
    Filed: March 25, 1986
    Date of Patent: June 9, 1987
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Nobuo Tanba, Nobuyuki Gotoo, Kazunori Onozawa, Atsushi Hiraishi