Abstract: An image processing device includes a multiplier 1 for multiplying a pixel signal P(x) by a weighting factor ?0 (0??0?1), a delay element 2 for delaying the pixel signal P(x) which has not been multiplied yet by the weighting factor ?0 by the multiplier 1 by one pixel, and a multiplier 3 for multiplying the pixel signal P(x?1) delayed by the delay element 2 by a weighting factor ?1 (0??1?1), the total sum of the weighting factors ?0 and ?1 being larger than 1 and smaller than an upper limit ?max. An adder 4 adds the multiplication result ?0·P(x) of the multiplier 1 and the multiplication result ?1·P(x?1) of the multiplier 3, and a limiter 5 limits the addition result P?(x) of the adder 4 in such a way that P?(x) falls within a maximum density value Pmax.

Abstract: A display unit has an image presentation section 10 for receiving a plurality of monomedia data and presentation style data describing a presentation style of a frame of each of the individual monomedia data, for generating scaling/combining control information 111 for combining the individual monomedia data, and for generating a composite video frame 103 by combining the individual monomedia data; an image enhancing section 20 for obtaining a correction target region of designated monomedia data in the composite video frame 103 in response to the scaling/combining control information 111, for generating correction data by obtaining interframe difference in the correction target region, and for generating a display video frame 104 by carrying out image enhancing processing of the correction target region in response to the correction data generated; and an image display section 30 for displaying the display video frame 104.

Abstract: In a display panel, a conductive member subjected to a prescribed electric potential lower than an anode potential is disposed on a first insulating substrate at a location spaced apart from an anode terminal subjected to the anode potential. An insulating member is disposed on the conductive member such that the insulating member includes a part located closer to the anode terminal than an end, on a side facing the anode terminal, of the conductive member and such that a gap is provided between the part and the first insulating substrate.

Abstract: An image display apparatus includes an envelope, first to third electroconductive members disposed in the envelope, a plate-like spacer disposed between the first and third members and between the second and third members, and a circuit for supplying a potential to the first member and supplying a potential lower than that of the first member to the second and third members. When a sheet resistance between a first region of the spacer to which the potential is supplied from the first member and a second region of the spacer to which the potential is supplied from the second member is defined as ?f [?/?] and a sheet resistance between a third region of the spacer to which the potential is supplied from the third member and a region located between the first and second regions is defined as ?r [?/?], a condition 1/100<?r/?f?40 is satisfied.

Abstract: An image processing device includes a car navigation processing unit 12 for processing a WQVGA signal, a TV receiving processing unit 15 for processing an NTSC signal, and an image resolution converting unit 17 which carries out an image resolution conversion of the NTSC signal from the TV receiving processing unit 15 to a WQVGA signal. The TV receiving processing unit 15 includes a pixel aspect ratio converting unit 104 for carrying out a pixel aspect ratio conversion of character data acquired from a WQVGA-ready character-font set 2, and a graphics/TV image compositing unit 106 for compositing an output from the pixel aspect ratio converting unit 104 with the NTSC signal, and for outputting a composite signal to the image resolution converting unit 17.

Abstract: A display unit has an image presentation section 10 for receiving a plurality of monomedia data and presentation style data describing a presentation style of a frame of each of the individual monomedia data, for generating scaling/combining control information 111 for combining the individual monomedia data, and for generating a composite video frame 103 by combining the individual monomedia data; an image enhancing section 20 for obtaining a correction target region of designated monomedia data in the composite video frame 103 in response to the scaling/combining control information 111, for generating correction data by obtaining interframe difference in the correction target region, and for generating a display video frame 104 by carrying out image enhancing processing of the correction target region in response to the correction data generated; and an image display section 30 for displaying the display video frame 104.

Abstract: An image display apparatus includes an envelope, first to third electroconductive members disposed in the envelope, a plate-like spacer disposed between the first and third members and between the second and third members, and a circuit for supplying a potential to the first member and supplying a potential lower than that of the first member to the second and third members. When a sheet resistance between a first region of the spacer to which the potential is supplied from the first member and a second region of the spacer to which the potential is supplied from the second member is defined as ?f [?/?] and a sheet resistance between a third region of the spacer to which the potential is supplied from the third member and a region located between the first and second regions is defined as ?r [?/?], a condition 1/100<?r/?f?40 is satisfied.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate which is capacitively coupled to the floating gate via a second insulating film. The first insulating film includes a first gate insulating film portion formed in the first surface region, and, a second gate insulating film portion formed in the step side region and the second surface region.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: The nonvolatile semiconductor memory device of the invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first and second surface regions; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; and a control gate capacitively coupled to the floating gate via a second insulating film. The first surface region is an upper surface of an epitaxially grown layer formed on the second surface region.

Abstract: The nonvolatile semiconductor memory device of the present invention includes: a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together; a channel region formed in the first surface region of the semiconductor substrate; a source region and a drain region which are formed in the surface of the semiconductor substrate so as to interpose the channel region therebetween; a first insulating film formed on the surface of the semiconductor substrate; a floating gate formed on the first insulating film; a second insulating film formed on the floating gate; and a control gate which is capacitively coupled to the floating gate via the second insulating film.

Abstract: A method for fabricating a nonvolatile semiconductor memory device according to the present invention includes the steps of: forming a first mask to define a channel of a memory cell in a semiconductor substrate; doping an impurity into the semiconductor substrate by using the first mask, thereby forming a first doped region in the semiconductor substrate; forming a second mask so as to overlap at least one of a first region of the semiconductor substrate where a source is to be formed and a second region of the semiconductor substrate where a drain is to be formed and at least part of the first mask; etching the semiconductor substrate by using the first and second masks, thereby forming a recessed portion in a region of the semiconductor substrate that is not covered with the first and second masks; forming a second doped region in the recessed portion of the semiconductor substrate; and removing the first and second masks, and forming a gate structure including a first insulating film, a floating gate elec

Abstract: In a semiconductor substrate having a surface including a first surface region at a first level, a second surface region at a second level lower than the first level, and a step side region linking the first surface region and the second surface region together, a channel region has a triple structure. Thus, a high electric field is formed in a corner portion between the step side region and the second surface region and in the vicinity thereof. A high electric field is also formed in the first surface region. As a result, the efficiency, with which electrons are injected into a floating gate, is considerably increased.

Abstract: In a semiconductor apparatus having a PNP bipolar transistor and high voltage resistance, there is formed an oxide insulating layer in the surface region of a P-type semiconductor substrate. In the above semiconductor substrate is formed a P-type collector layer so that at least a part of the P-type collector layer is in contact with said oxide insulating layer. In the surface region of said P-type collector layer is formed a P-type collector contact layer. An N-type base layer is formed in that region on the surface side of said P-type collector layer in which said P-type collector contact layer does not exist. A P-type emitter layer is formed on the surface side of said N-type base layer.