Patents by Inventor Atsushi Iijima

Atsushi Iijima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130241081
    Abstract: A main package includes a plurality of stacked semiconductor chips and a plurality of first terminals associated with different ones of the semiconductor chips. An additional package includes an additional semiconductor chip and at least one second terminal electrically connected to the additional semiconductor chip. The additional semiconductor chip is to substitute for one of the plurality of semiconductor chips in the main package. The main package and the additional package are arranged in one of a plurality of relative positional relationships that is selected according to which one of the plurality of semiconductor chips in the main package is to be substituted with the additional semiconductor chip.
    Type: Application
    Filed: March 16, 2012
    Publication date: September 19, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Atsushi IIJIMA
  • Patent number: 8536712
    Abstract: A memory device has a laminated chip package and a controller plate. In the laminated chip package, a plurality of memory chips are laminated. An interposed chip is laminated between the laminated chip package and the controller plate. A plurality of opposing wiring electrodes are formed at an opposing surface of the controller plate. A plurality of outside wiring electrodes are formed on the rear side of the opposing surface. Connection electrodes connecting the opposing wiring electrodes and the outside wiring electrodes are formed on the side surface of the controller plate. The interposed chip has a plurality of interposed wiring electrodes. The plurality of interposed wiring electrodes are formed with a common arrangement pattern common with an arrangement pattern of the plurality of opposing wiring electrodes. The controller plate is laid on the interposed chip.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: September 17, 2013
    Assignees: SAE Magnetics Ltd., Headway Technologies, Inc.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8525167
    Abstract: In a laminated chip package, a plurality of semiconductor plates each having a semiconductor device and a wiring electrode connected to the semiconductor device are laminated. On a side surface for wiring of the laminated chip package, an end face of an inner electrode for examination formed inside the side surface for wiring in the semiconductor plate is formed. The laminated chip package further has an outer electrode for examination connecting the end faces of the inner electrodes for examination along a lamination direction of the semiconductor plates, only for two adjacent semiconductor plates among the semiconductor plates.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: September 3, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8514520
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The write shield layer has an opposing shield part opposing the main magnetic pole layer and a front shield part. The front shield part is connected to the opposing shield part without straddling the thin-film coil. Besides, the front shield part has a shield front end face disposed in the medium-opposing surface and a shield upper end face formed distanced from the medium-opposing surface. Further, the front shield part has a shield connecting part. The shield front end face is connected to the shield upper end face by the shield connecting part.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: August 20, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Patent number: 8514516
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, a thin-film coil and a shield magnetic layer are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. This thin-film magnetic head has a hard guard frame layer surrounding an equidistant coil part, disposed at a position equidistant from the substrate, from outside and being in direct contact with almost a whole outside surface defining an outer shape of the equidistant coil part.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: August 20, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hironori Araki, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Patent number: 8499435
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a lower shield layer, an upper shield layer and a thin-film coil are laminated on a substrate. A method of manufacturing the thin-film magnetic head has a lower shield layer forming step. This step comprises a step of forming a first lower shield part in a lower shield planned area, including a planned line along the medium-opposing surface, a step of forming a partial lower seed layer having a partial arrangement structure in which the partial lower seed layer is arranged on a lower formation zone except a lower exception zone including the planned line, a step of forming a second lower shield part on the partial lower seed layer.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: August 6, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Patent number: 8498080
    Abstract: A magnetic head includes a main pole, a write shield, a return path section, a heater that generates heat for making part of a medium facing surface protrude, and a sensor that detects contact of the part of the medium facing surface with a recording medium. The return path section includes: a yoke layer located backward of the main pole along the direction of travel of the recording medium; a first coupling part coupling the yoke layer and the write shield to each other; and a second coupling part located away from the medium facing surface and coupling the yoke layer and the main pole to each other. The first coupling part has an end face facing toward the yoke layer. This end face includes a middle portion spaced from the yoke layer and facing the yoke layer, and two side portions located on opposite sides of the middle portion in a track width direction and in contact with the yoke layer. The sensor is located between the middle portion and the yoke layer.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: July 30, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Patent number: 8493687
    Abstract: A magnetic head includes a shield, and first and second return path sections. The shield has an end face that is located in a medium facing surface to wrap around an end face of a main pole. The shield includes a bottom shield, two side shields, and a top shield. The first return path section includes a yoke layer, and first and second coupling layers that magnetically couple the bottom shield and the yoke layer to each other. The first coupling layer is magnetically connected to the bottom shield. The second coupling layer magnetically couples the first coupling layer to the yoke layer. No end faces of the second coupling layer are exposed in the medium facing surface. The second return path section magnetically couples the top shield and the main pole to each other.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: July 23, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Publication number: 20130176644
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, a thin-film coil and a shield magnetic layer are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. This thin-film magnetic head has a hard guard frame layer surrounding an equidistant coil part, disposed at a position equidistant from the substrate, from outside and being in direct contact with almost a whole outside surface defining an outer shape of the equidistant coil part.
    Type: Application
    Filed: January 5, 2012
    Publication date: July 11, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Hironori ARAKI, Shigeki TANEMURA, Kazuki SATO, Atsushi IIJIMA
  • Patent number: 8482105
    Abstract: A semiconductor substrate has a plurality of groove portions formed along scribe lines. The semiconductor substrate includes: a unit region in contact with at least any one of the plurality of groove portions; and a wiring electrode with a portion thereof arranged within the unit region. Further, the plurality of groove portions have a wide-port structure in which a wide width portion wider in width than a groove lower portion including a bottom portion is formed at an inlet port thereof.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: July 9, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima
  • Patent number: 8477452
    Abstract: A bottom end of a main pole includes first, second, and third portions that are contiguously arranged in order of increasing distance from the medium facing surface. A top surface of the main pole includes fourth, fifth, and sixth portions that are contiguously arranged in order of increasing distance from the medium facing surface. A distance from the top surface of the substrate to any given point on each of the first and second portions decreases with increasing distance from the given point to the medium facing surface. The second portion has an angle of inclination greater than that of the first portion with respect to a direction perpendicular to the medium facing surface. A distance from the top surface of the substrate to any given point on each of the fourth and fifth portions increases with increasing distance from the given point to the medium facing surface.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: July 2, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Shigeki Tanemura, Hironori Araki, Atsushi Iijima
  • Publication number: 20130155550
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a write shield layer, a gap layer, and a thin-film coil are laminated on a substrate. The thin-film magnetic head has a shield magnetic layer. The shield magnetic layer has a leading shield part. The leading shield part is disposed on a substrate side of the main magnetic pole layer. The leading shield part has a variable distance structure in which a rearmost part most distanced from the medium-opposing surface is distanced more from the main magnetic pole layer than is a foremost part on the main magnetic pole layer side.
    Type: Application
    Filed: December 16, 2011
    Publication date: June 20, 2013
    Applicants: HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Shigeki Tanemura, Kazuki Sato, Atsushi Iijima
  • Patent number: 8466562
    Abstract: A layered chip package includes a plurality of layer portions that are stacked, each of the layer portions including a semiconductor chip. The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The semiconductor chip has a circuit, a plurality of electrode pads electrically connected to the circuit, and a plurality of through electrodes. In every vertically adjacent two of the layer portions, the plurality of through electrodes of the semiconductor chip of one of the two layer portions are electrically connected to the respective corresponding through electrodes of the semiconductor chip of the other of the two layer portions. The first-type layer portion includes a plurality of wires for electrically connecting the plurality of through electrodes to the respective corresponding electrode pads, whereas the second-type layer portion does not include the wires.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: June 18, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Patent number: 8462482
    Abstract: In a ceramic capacitor according to the present invention, an interdiginated pair of internal electrodes are arranged, on a substrate, perpendicular to a surface of the substrate, and a ceramic dielectric member is filled into a gap between this pair of internal electrodes. For this reason, the dimensions of the internal electrodes do not substantially change before and/or after the formation of the ceramic dielectric member, whereby the dimensions formed at the time of internal electrode can be maintained. According to this ceramic capacitor, since the internal electrode dimensions can be easily controlled like this, dimensional control of internal electrode spacing can also be easily carried out.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: June 11, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K) Ltd.
    Inventors: Yoshitaka Sasaki, Atsushi Iijima, Hiroshi Ikejima
  • Patent number: 8455349
    Abstract: A layered chip package includes a main body and a plurality of through electrodes. The main body includes a plurality of layer portions stacked and a plurality of through holes that penetrate all the plurality of layer portions. The plurality of through electrodes are provided in the plurality of through holes of the main body and penetrate all the plurality of layer portions. Each of the plurality of layer portions includes a semiconductor chip. At least one of the plurality of layer portions includes wiring that electrically connects the semiconductor chip to the plurality of through electrodes. The wiring includes a plurality of conductors that make contact with a through electrode that is exposed in the wall faces of any one of the plurality of through holes and passes through the through hole.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: June 4, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd., TDK Corporation
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Atsushi Iijima, Tatsuya Harada
  • Patent number: 8441755
    Abstract: A magnetic head includes: a main pole; a coil; a first shield having an end face that is located in a medium facing surface at a position forward of an end face of the main pole along a direction of travel of a recording medium; and a first return path section disposed forward of the main pole along the direction of travel of the recording medium. The first return path section connects part of the main pole away from the medium facing surface to the first shield so that a first space is defined. The coil includes a first portion having a planar spiral shape and wound around a core part of the first return path section. The first portion includes first and second coil elements that each extend through the first space. No part of the coil other than the first and second coil elements exists in the first space.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: May 14, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Kazuki Sato, Atsushi Iijima
  • Patent number: 8441112
    Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes: a main part including first and second layer portions; and a plurality of first and second terminals that are disposed on the top and bottom surfaces of the main part, respectively, and are electrically connected to the plurality of wires. The first and second terminals are formed by using electrodes of the first and second layer portions. The layered chip package is manufactured by fabricating a layered substructure by stacking two substructures each of which includes an array of a plurality of preliminary layer portions, and then cutting the layered substructure. The layered substructure includes a plurality of preliminary wires that are disposed between two adjacent pre-separation main bodies and are to become the plurality of wires.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: May 14, 2013
    Assignees: Headway Technologies, Inc., Sae Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Hiroyuki Ito, Hiroshi Ikejima, Atsushi Iijima
  • Publication number: 20130105949
    Abstract: In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions having a semiconductor device formed therein and insulated from each other, and a plurality of wiring electrodes connected to the semiconductor devices respectively formed in the plurality of device regions and extending from the device regions into the inside of the scribe-groove parts. The plurality of wiring electrodes are arranged in a partial arrangement pattern in which the wiring electrodes are arranged along only a part of four boundary sides, corresponding to boundaries between each of the device regions and the scribe-groove parts. Further, the plurality of wiring electrodes extend into the scribe-groove part from only one of two device regions adjacent to each other with the scribe-groove part therebetween.
    Type: Application
    Filed: November 1, 2011
    Publication date: May 2, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Shigeki TANEMURA, Kazuki SATO, Atsushi IIJIMA
  • Patent number: 8432662
    Abstract: In a ceramic capacitor according to the present invention, the electrode strips of an internal electrode and the dielectric strips of a ceramic dielectric member are arranged perpendicularly to the surface of a substrate, and as such, the plurality of electrode strips and the plurality of dielectric strips are arranged alternately along a parallel direction relative to the substrate surface. That is, the electrode strips and the dielectric strips are multi-layered along a parallel direction relative to the substrate surface, thereby facilitating the realization of multi-layering in the ceramic capacitor by a known patterning technology.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: April 30, 2013
    Assignees: Headway Technologies, Inc., SAE Magnetics (H.K.) Ltd.
    Inventors: Yoshitaka Sasaki, Atsushi Iijima, Hiroshi Ikejima
  • Publication number: 20130100555
    Abstract: A thin-film magnetic head is constructed such that a main magnetic pole layer, a lower shield layer, an upper shield layer and a thin-film coil are laminated on a substrate. A method of manufacturing the thin-film magnetic head has a lower shield layer forming step. This step comprises a step of forming a first lower shield part in a lower shield planned area, including a planned line along the medium-opposing surface, a step of forming a partial lower seed layer having a partial arrangement structure in which the partial lower seed layer is arranged on a lower formation zone except a lower exception zone including the planned line, a step of forming a second lower shield part on the partial lower seed layer.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 25, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., HEADWAY TECHNOLOGIES, INC.
    Inventors: Yoshitaka SASAKI, Hiroyuki ITO, Shigeki TANEMURA, Kazuki SATO, Atsushi IIJIMA