Abstract: A semiconductor device includes: a substrate; and wiring layers on the substrate. Each wiring layer includes: an interlayer insulation film having a wiring groove with a via hole; a copper wiring in the groove and the hole; an barrier metal layer between an inner wall of the groove with the hole and the copper wiring; and an upper barrier metal layer on the interlayer insulation film and covering an upper surface of the copper wiring. The barrier metal layer prevents a copper component in the copper wiring from diffusing into the interlayer insulation film. The copper wiring of an upper layer is electrically coupled with the copper wiring of a lower layer. The upper barrier metal layer of the lower layer prevents a copper component in the copper wiring of the lower layer from diffusing into the interlayer insulation film of the upper layer.

Abstract: This invention provides a long-life Sialon insert, the cutting edge of which is resistant to wear and hard to fracture, and a cutting tool equipped with the Sialon insert. Provided are a Sialon insert made of a Sialon sintered body including a Sialon phase comprising an ?-Sialon and a ?-Sialon, and at least one element, originating from a sintering aid, selected from the group consisting of Sc, Y, Dy, Yb, and Lu in an amount of 0.5 to 5 mol % in terms of an oxide thereof, wherein an ?-value, which shows the proportion of the ?-Sialon in the Sialon phase, is from 10% to 40%; the ?-Sialon has a value of Z from 0.2 to 0.7 wherein Z is a variable of the formula Si6-ZAlZOZN8-Z and within a range: 0<Z?4.2; and the sintered body has an average thermal expansion coefficient of 3.5×10?6/K or less at temperatures of room temperature to 1000° C., and a thermal conductivity of 10 W/m·K or more at temperatures of room temperature to 1000° C., and a cutting tool comprising a holder equipped with the Sialon insert.

Abstract: A semiconductor device includes a substrate, an element formed in the substrate, an insulation film formed on the substrate, wiring layers, and an electrode pad. The wiring layers are multilayered and electrically coupled to the element through the insulation film. The electrode pad is electrically coupled to a top wiring layer of the wiring layers. The top wiring layer is configured to be a top wiring-electrode layer that doubles as an electrode layer disposed under the electrode pad. The electrode layer of the top wiring-electrode layer is disposed directly above the element. The electrode pad and the electrode layer are multilayered to form a pad structure.

Abstract: A dicing sheet frame, which is used when a semiconductor wafer adhered to a dicing sheet is cut into chips, includes a plurality of frame parts and a connecting device. The plurality of frame parts supports the dicing sheet. The connecting device connects the plurality of frame parts such that the plurality of frame parts has an annular shape.

Abstract: A method for dicing a semiconductor substrate includes: forming a reforming layer in the substrate by irradiating a laser beam on the substrate; forming a groove on the substrate along with a cutting line; and applying a force to the substrate in order to cutting the substrate at the reforming layer as a starting point of cutting. The groove has a predetermined depth so that the groove is disposed near the reforming layer, and the force provides a stress at the groove.

Abstract: A device separated from a wafer includes: a chip having a sidewall, which is provided by a dicing surface of the wafer in a case where the device is separated from the wafer; and a protection member disposed on the sidewall of the chip for protecting the chip from being contaminated by a dust from the dicing surface. In the device, the dicing surface of the wafer is covered with the protection member so that the chip is prevented from contaminated with the dust.

Abstract: In a process of manufacturing a semiconductor device, after a gate oxide film is formed, the thickness of the gate oxide film is measured by measuring an exposure period defined from a time at which the oxide film is formed to a time at which the thickness of the oxide film is measured. In addition, if necessary, the measurement of the oxide film is corrected to determine the real thickness based on the exposure period. Accordingly, the thickness of the gate oxide film can be measured accurately.

Abstract: The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 &mgr;m, the number of Al voids with widths of over 0.3 &mgr;m is practically reduced to 0.

Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.

Abstract: The purpose of the present invention is to obtain an electrode wiring structure for semiconductor devices that can suppress the occurrence of Al voids inside aluminum alloy wiring without regard to the orientation of such aluminum alloy wiring. An interlayer insulator film 11, a titanium layer 12, a titanium nitride layer 13 that serves as the barrier layer, an aluminum alloy wiring layer 15 and a protective film 18 are formed on top of the silicon substrate 10 to compose the electrode structure. In this case, a distortion relaxation layer 14, with a film thickness of approximately over 10 nm and which is an intermetallic compound that includes aluminum and titanium in its composition, is formed in between the titanium nitride layer 13 and the aluminum alloy wiring layer 15. Because of this distortion relaxation layer, for every wiring width of 1 .mu.m, the number of Al voids with widths of over 0.3 .mu.m is practically reduced to 0.

Abstract: A process for forming trenches on a surface of a semiconductor substrate by dry etching using a gas mixture. The gas mixture comprises; (1) an etchant gas comprising at least bromine which etches the semiconductor surface to form trenches, (2) a cleaning gas comprising a halogen which evaporates residue formed by the etching, and (3) a reactive gas, e.g. N.sub.2, capable of reacting with material formed during the etching and capable of controlling the inclination of the trenches.

Abstract: An object of the invention is to prevent the occurrence of breaking or short-circuiting of a wiring caused by a difference in level in an isolation trench area formed in an SOI substrate. An oxide film is formed for a pad on the main surface of an SOI layer formed on an insulating substrate, a silicon nitride film are formed and an SiO.sub.2 film in order, then an isolation trench reaching to the insulating substrate is by means of an R.I.E process using the SiO.sub.2 film as a mask. Thereafter an insulating film is formed on an inside wall of the isolation trench by means of thermal oxidation, the isolation trench is filled with polysilicon, the polysilicon is etched back while controlling the etching so that the top of the polysilicon in the isolation trench remains higher than the top of the silicon nitride film, an extra part of the polysilicon deposited on the surface of the substrate, is removed and then the SiO.sub.

Abstract: A process for forming deep trenches on a surface of a semiconductor substrate by forming a mask on the surface of the semiconductor, which prescribes the position of the trenches; and then dry etching the semiconductor surface using a gas mixture comprising (1) an etchant, bromine containing, gas which etches the semiconductor surface to form trenches, (2) a cleaning, halogen containing, gas which evaporates the residue formed by the etching; and (3) a reactive gas capable of reacting with material formed during the etching and capable of decreasing the wastage of the mask by the etchant gas.

Abstract: An aluminum line including nitrogen formed as a film in a semiconductor integrated circuit is disclosed. Each crystal grain size of the aluminum line is lower than or equal to 0.3 .mu.m to suppress electromigration. A method of forming the aluminum line which can supress electromigration is also disclosed. The amount of an inert gas Q and the amount of a nitrogen gas Q.sub.N are controlled to satisfy "2.ltoreq.(Q.sub.N /Q).times.100.ltoreq.10".