Atsushi Kunimatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An information processing apparatus secures a wide band width in a graphics bus and draws graphics at high speed and low cost. The apparatus employs graphics processing units connected in parallel. Each of the units is formed on a chip and has a graphics processor and a graphics memory, to provide color information and select information. The outputs of the units are selected through a tournament.
Abstract: A stall detecting apparatus and a stall detecting method reduce labor and time to develop a program.
The apparatus has an input portion for reading a source program, an interpreter for interpreting the read source program according to processor specifications, an instruction developing unit for developing the interpreted source program into states in pipeline stages of pipeline processing, and a stall detector for detecting stalls in the pipeline processing according to the states of the source program developed in the pipeline stages and providing stall information representing the detected stalls. The stall detecting method realizes these functions of the stall detecting apparatus. The method and apparatus statically analyze a given source program while the source program is being coded and efficiently detect stalls to occur in the source program. The method and apparatus display the stall information together with the source program and a pipeline image of the pipeline processing of the source program.
Abstract: A geometry translation processor used when drawing a polygon on a display translates coordinates and efficiently carries out a clipping test to determine whether or not the polygon must be clipped on the display. The processor has operation units (5x, 5y, 5z), clipping comparators (4x, 4y, 4z) provided for the operation units, respectively, and a clipping register (6). The clipping comparators compare the elements (xn, yn, zn) of a translated coordinate vector with the remaining element (wn) of the same vector. The clipping register is used to store the outputs of the clipping comparators and speedily carry out the clipping test.
Abstract: An instruction code is received by an instruction input section 103 and then decoded by the instruction decode section 105 to generate an operand and control signals. The instruction division control section 109 generates a division control signal based on the control signals and an operand selection section 107 generates an operand having a desired bit width by using the operand from the instruction decode section 105 based on the division control signal. An arithmetic section 111 divides the operand into a desired bit width parts based on the division control signal and performs arithmetic operation. A memory access control section 115 receives calculated address and transfers this calculated address and the division control signal to a memory. The memory access control section 115 receives data from the memory and transfers the data into the arithmetic result store section 113.