Patents by Inventor Atsushi Kurokawa

Atsushi Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227941
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: January 18, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 11203388
    Abstract: A bicycle electric suspension comprises a first tube, a second tube, a positioning structure, an electric positioning actuator, and a telescopic controller. The first tube has a center axis. The second tube is telescopically received in the first tube. The positioning structure is configured to relatively position the first tube and the second tube in a telescopic direction extending along the center axis of the first tube. The electric positioning actuator is configured to actuate the positioning structure. The telescopic controller has a pairing signal transmission mode in which the telescopic controller transmits a pairing signal to a bicycle electric device.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: December 21, 2021
    Assignee: SHIMANO INC.
    Inventors: Atsushi Komatsu, Takafumi Nishino, Yuta Kurokawa
  • Publication number: 20210391429
    Abstract: A mesa portion is formed on a substrate. An insulating film including an organic layer is disposed on the mesa portion. A conductor film is disposed on the insulating film. A cavity provided in the organic layer has side surfaces extending in a first direction. A shorter distance out of distances in a second direction perpendicular to the first direction from the mesa portion to the side surfaces of the cavity in plan view is defined as a first distance. A shorter distance out of distances in the first direction from the mesa portion to side surfaces of the cavity in plan view is defined as a second distance. A height of a first step of the mesa portion is defined as a first height. At least one of the first distance and the second distance is greater than or equal to the first height.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi KUROKAWA, Masahiro SHIBATA, Hiroaki TOKUYA, Mari SAJI
  • Publication number: 20210391233
    Abstract: A first layer conductor film is connected to an operation electrode through an opening in a first layer interlayer insulating film. An opening in a second layer interlayer insulating film is encompassed by the first layer conductor film in plan view. A second layer conductor film is connected to the first layer conductor film through the opening in a second layer interlayer insulating film. The average, along a first direction, of distances in a second direction, which is perpendicular to the first direction, from the opening in the first layer interlayer insulating film to the side surface of the opening in the second layer interlayer insulating film is greater than or equal to a distance in a height direction from an upper opening plane of the opening in the first layer interlayer insulating film to a lower opening plane of the opening in the second layer interlayer insulating film.
    Type: Application
    Filed: June 11, 2021
    Publication date: December 16, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Mari SAJI, Masahiro SHIBATA, Atsushi KUROKAWA
  • Patent number: 11158592
    Abstract: Transistors including semiconductor regions where operating current flows are provided above a substrate. Operating electrodes of conductive material having thermal conductivity higher than the semiconductor regions and contacting the semiconductor regions to conduct operating current to the semiconductor regions are disposed. A conductor pillar for external connection contains contact regions where the semiconductor regions and the operating electrodes contact, and is electrically connected to the operating electrodes. The contact regions are disposed in a first direction. Each contact region has a planar shape long in a second direction orthogonal to the first direction. A first average distance, obtained by averaging distances in the second direction from each end portion of the contact region in the second direction to an edge of the conductor pillar across the contact regions, exceeds an average distance value in a height direction from the contact region to a top surface of the conductor pillar.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masahiro Shibata, Atsushi Kurokawa
  • Publication number: 20210242842
    Abstract: A power amplifier circuit includes a first transistor disposed on a semiconductor substrate; a second transistor disposed on the semiconductor substrate and configured to supply a bias current based on a first current which is a part of a control current to the first transistor; a third transistor disposed on the semiconductor substrate and having a collector configured to be supplied with a second current which is a part of the control current and an emitter configured to output a third current based on the second current; a first bump electrically connected to an emitter of the first transistor and disposed so as to overlap a first disposition area in which the first transistor is disposed in plan view of the semiconductor substrate; and a second bump disposed so as to overlap a second disposition area in which the third transistor is disposed in the plan view.
    Type: Application
    Filed: February 5, 2021
    Publication date: August 5, 2021
    Inventors: Hiroaki TOKUYA, Hideyuki SATO, Fumio HARIMA, Kenichi SHIMAMOTO, Satoshi TANAKA, Takayuki KAWANO, Ryoki SHIKISHIMA, Atsushi KUROKAWA
  • Patent number: 11081573
    Abstract: A semiconductor element includes a semiconductor substrate; a collector layer on the semiconductor substrate; a base layer on the collector layer; an emitter layer on the base layer; emitter wiring electrically coupled to the emitter layer; a top metal layer on the emitter wiring; a first protective film covering the emitter wiring and the top metal layer, the first protective film having a first opening that overlaps at least the collector layer; and a bump including an under-bump metal layer electrically coupled to the emitter wiring via the first opening, the under-bump metal layer being larger than the first opening in plan-view area. The first protective film has an inner edge around the first opening, and the inner edge is on the top metal layer.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 3, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Kazuya Kobayashi
  • Publication number: 20210234026
    Abstract: A bipolar transistor comprising a subcollector layer, and a collector layer on the subcollector layer. The collector layer includes a plurality of doped layers. The plurality of doped layers includes a first doped layer that has a highest impurity concentration thereamong and is on a side of or in contact with the subcollector layer. Also, the first doped layer includes a portion that extends beyond at least one edge of the plurality of doped layers in a cross-sectional view.
    Type: Application
    Filed: April 13, 2021
    Publication date: July 29, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Patent number: 11056423
    Abstract: A semiconductor device includes a semiconductor chip mounted to a mounting substrate with an interposer interposed therebetween such that a surface of the semiconductor chip on which bumps are formed faces a surface of the mounting substrate. The mounting substrate has a plurality of metal parts formed as terminals on a surface of the mounting substrate and in contact with electrode pads connected to multilayer wiring. The semiconductor chip has a plurality of functional elements formed in an inner layer and a plurality of bumps formed in contact with element wiring lines of the functional elements such that the bumps protrude from the surface of the semiconductor chip. The interposer has a plurality of first recesses formed in the surface of the interposer facing the surface of the semiconductor chip on which the bumps are formed such that the first recesses accommodate only the bumps.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: July 6, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichi Sano, Atsushi Kurokawa
  • Publication number: 20210126116
    Abstract: A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Atsushi KUROKAWA
  • Patent number: 10985123
    Abstract: A first wiring is disposed above operating regions of plural unit transistors formed on a substrate. A second wiring is disposed above the substrate. An insulating film is disposed on the first and second wirings. First and second cavities are formed in the insulating film. As viewed from above, the first and second cavities entirely overlap with the first and second wirings, respectively. A first bump is disposed on the insulating film and is electrically connected to the first wiring via the first cavity. A second bump is disposed on the insulating film and is electrically connected to the second wiring via the second cavity. As viewed from above, at least one of the plural operating regions is disposed within the first bump and is at least partially disposed outside the first cavity. The planar configuration of the first cavity and that of the second cavity are substantially identical.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: April 20, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui
  • Patent number: 10950548
    Abstract: A semiconductor device includes electrodes which contain Au and which are placed above conductive layers in a region adjacent to stacked insulating films and also includes base layers which are composed of compositionally modulated layers and which are placed between the electrodes and the conductive layers. The base layers include lateral end sections composed of single layers projecting from lateral end sections of the electrodes in the direction of the interlayer interface between the insulating films; sections which are located under the electrodes and of which a major compositional component is Ti or Ti and W; and projecting sections which project from under the electrodes in the direction of the interlayer interface between the insulating films and of which compositional components are compositionally modulated to Ti and O, to Ti, O, and N, or to Ti, W, O, and N.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: March 16, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yuichi Sano, Atsushi Kurokawa, Kazuya Kobayashi
  • Publication number: 20210035922
    Abstract: At least one unit transistor is arranged over a substrate. A first wiring as a path of current that flows to each unit transistor is arranged over the at least one unit transistor. An inorganic insulation film is arranged over the first wiring. At least one first opening overlapping a partial region of the first wiring in a plan view is provided in the inorganic insulation film. An organic insulation film is arranged over the inorganic insulation film. A second wiring coupled to the first wiring through the first opening is arranged over the organic insulation film and the inorganic insulation film. In a plan view, a region in which the organic insulation film is not arranged is provided outside a region in which the first wiring is arranged. The second wiring is in contact with the inorganic insulation film outside the region in which the first wiring is arranged.
    Type: Application
    Filed: July 30, 2020
    Publication date: February 4, 2021
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki TOKUYA, Masahiro SHIBATA, Akihiko OZAKI, Satoshi GOTO, Fumio HARIMA, Atsushi KUROKAWA
  • Patent number: 10903343
    Abstract: A semiconductor device includes an HBT; emitter wiring which is connected to an emitter electrode of the HBT and covers the HBT; a passivation film having an opening on the HBT in plan view; a UBM layer which is connected to the emitter wiring through the opening and made of a refractory metal with a thickness of 300 nm or more; and a pillar bump which is arranged on the UBM layer and includes a metal post and a solder layer. The UBM layer serves as a stress relaxation layer, thereby relaxing stress on the HBT due to a difference in thermal expansion coefficient between a GaAs-based material of each layer constituting the HBT and the pillar bump.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: January 26, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Atsushi Kurokawa
  • Patent number: 10892350
    Abstract: A semiconductor device includes a semiconductor element including a bipolar transistor disposed on a compound semiconductor substrate, a collector electrode, a base electrode, and an emitter electrode, the bipolar transistor including a collector layer, a base layer, and an emitter layer, the collector electrode being in contact with the collector layer, the base electrode being in contact with the base layer, the emitter electrode being in contact with the emitter layer; a protective layer disposed on one surface of the semiconductor element; an emitter redistribution layer electrically connected to the emitter electrode via a contact hole in the protective layer; and a stress-relieving layer disposed between the emitter redistribution layer and the emitter layer in a direction perpendicular to a surface of the compound semiconductor substrate.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kurokawa, Yuichi Sano
  • Publication number: 20200335611
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Application
    Filed: July 2, 2020
    Publication date: October 22, 2020
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari UMEMOTO, Shigeki KOYA, Atsushi KUROKAWA
  • Publication number: 20200291271
    Abstract: Provided is a release sheet including a substrate and a release layer, wherein the release layer is composed of a crosslinked product of a resin composition containing a polyolefin resin having a reactive functional group and a crosslinking agent; and the content of the polyolefin resin having a reactive functional group is from 50 to 90% by mass, and the content of the crosslinking agent is from 7 to 45% by mass, relative to the whole amount of the resin composition.
    Type: Application
    Filed: September 11, 2017
    Publication date: September 17, 2020
    Applicant: LINTEC Corporation
    Inventors: Koji MIYAMOTO, Atsushi KUROKAWA, Masayasu KAMO
  • Patent number: 10777667
    Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Atsushi Kurokawa, Koshi Himeda, Kazuya Kobayashi
  • Patent number: 10741680
    Abstract: A bipolar transistor has a subcollector layer and a stack of collector, base, and emitter layers on the subcollector layer. On the subcollector layer are collector electrodes. On the base layer are base electrodes. The collector layer includes multiple doped layers with graded impurity concentrations, higher on the subcollector layer side and lower on the base layer side. Of these doped layers, the one having the highest impurity concentration is in contact with the subcollector layer and has a sheet resistance less than or equal to about nine times that of the subcollector layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 11, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasunari Umemoto, Shigeki Koya, Atsushi Kurokawa
  • Patent number: 10734310
    Abstract: A wiring is disposed above operating regions of plural unit transistors arranged on a substrate in a first direction. An insulating film is disposed on the wiring. A cavity entirely overlapping with the wiring as viewed from above is formed in the insulating film. A metal member electrically connected to the wiring via the cavity is disposed on the insulating film. The centroid of the cavity is displaced from that of the operating region of the corresponding unit transistor in the first direction. When the cavity having a centroid the closest to the operating region of a unit transistor is defined as the closest proximity cavity, the amount of deviation of the centroid of the closest proximity cavity from that of the operating region of the corresponding unit transistor in the first direction becomes greater from the center to the ends of the arrangement direction of the unit transistors.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 4, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kurokawa, Masayuki Aoike, Takayuki Tsutsui