Abstract: A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied.

Abstract: A semiconductor device includes a semiconductor substrate provided with a predetermined element and having wirings formed on its main surface connected to back wirings by a plurality of through silicon vias (TSVs), and a conductive cover which covers the main surface of the semiconductor substrate. The semiconductor substrate and the conductive cover are bonded to each other with a conductive bonding member. The TSV bonded to the conductive cover with the conductive bonding member is connected to an external electrode pad to which a ground potential is supplied.

Abstract: A nonvolatile semiconductor memory including: a plurality of stripe-shaped active regions extending in a bit line direction; device isolation regions having tops arranged at a location higher than the active regions; a plurality of word lines and select gate lines intersecting with the bit line direction; and memory cell transistors arranged at the intersections of the active regions and the word lines via gate insulator films, including floating gate electrodes formed on the device isolation regions and gate insulator films on the active regions, and isolated on the device isolation regions, control gate electrodes arranged on the floating gate electrodes, and inter-gate insulator films arranged between the control gate electrodes and the floating gate electrodes; wherein, the thickness of the floating gate electrodes on the active regions and a maximum thickness of the floating gate electrodes on the device isolation regions are substantially the same, and steps are provided at the edges of the floating gat

Abstract: A nonvolatile semiconductor memory including: a plurality of stripe-shaped active regions extending in a bit line direction; device isolation regions having tops arranged at a location higher than the active regions; a plurality of word lines and select gate lines intersecting with the bit line direction; and memory cell transistors arranged at the intersections of the active regions and the word lines via gate insulator films, including floating gate electrodes formed on the device isolation regions and gate insulator films on the active regions, and isolated on the device isolation regions, control gate electrodes arranged on the floating gate electrodes, and inter-gate insulator films arranged between the control gate electrodes and the floating gate electrodes; wherein, the thickness of the floating gate electrodes on the active regions and a maximum thickness of the floating gate electrodes on the device isolation regions are substantially the same, and steps are provided at the edges of the floating gat