Patents by Inventor Atsushi Nishikizawa

Atsushi Nishikizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10643930
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: May 5, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa, Hiroyuki Nakamura
  • Patent number: 10522446
    Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: December 31, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nishikizawa, Tadatoshi Danno
  • Patent number: 10347567
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 9, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
  • Patent number: 10157878
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: December 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa
  • Publication number: 20180315685
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Application
    Filed: June 27, 2018
    Publication date: November 1, 2018
    Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
  • Patent number: 10083898
    Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Tsukasa Matsushita, Atsushi Nishikizawa
  • Patent number: 10037932
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: July 31, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Atsushi Nishikizawa, Yuichi Yato, Hiroi Oka, Tadatoshi Danno, Hiroyuki Nakamura
  • Publication number: 20180182692
    Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.
    Type: Application
    Filed: November 30, 2017
    Publication date: June 28, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Tadatoshi DANNO, Atsushi NISHIKIZAWA, Hiroyuki NAKAMURA
  • Publication number: 20180151479
    Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.
    Type: Application
    Filed: September 26, 2017
    Publication date: May 31, 2018
    Inventors: Atsushi NISHIKIZAWA, Tadatoshi DANNO
  • Publication number: 20180076115
    Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion.
    Type: Application
    Filed: November 20, 2017
    Publication date: March 15, 2018
    Inventors: Tadatoshi DANNO, Tsukasa MATSUSHITA, Atsushi NISHIKIZAWA
  • Patent number: 9837339
    Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion.
    Type: Grant
    Filed: March 19, 2017
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Tadatoshi Danno, Tsukasa Matsushita, Atsushi Nishikizawa
  • Publication number: 20170309550
    Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion.
    Type: Application
    Filed: March 19, 2017
    Publication date: October 26, 2017
    Inventors: Tadatoshi DANNO, Tsukasa MATSUSHITA, Atsushi NISHIKIZAWA
  • Publication number: 20170301643
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.
    Type: Application
    Filed: July 5, 2017
    Publication date: October 19, 2017
    Inventors: Tadatoshi DANNO, Atsushi NISHIKIZAWA
  • Patent number: 9735127
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: August 15, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tadatoshi Danno, Atsushi Nishikizawa
  • Publication number: 20170221800
    Abstract: In a resin sealing type semiconductor device, a semiconductor chip CP2 is mounted over a die pad DP having conductivity via a bonding member BD2 having insulation property, and a semiconductor chip CP1 is mounted over the die pad DP via a bonding member BD1 having conductivity. A first length of a portion, in a first side formed by an intersection of a first side surface and a second side surface of the semiconductor chip CP2, covered with the bonding member BD2 is larger than a second length of a portion, in a second side formed by an intersection of a third side surface and a fourth side surface of the semiconductor chip CP1, covered with the bonding member BD1.
    Type: Application
    Filed: March 30, 2015
    Publication date: August 3, 2017
    Inventors: Atsushi NISHIKIZAWA, Yuichi YATO, Hiroi OKA, Tadatoshi DANNO, Hiroyuki NAKAMURA
  • Publication number: 20170077069
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.
    Type: Application
    Filed: July 15, 2016
    Publication date: March 16, 2017
    Inventors: Tadatoshi DANNO, Atsushi NISHIKIZAWA
  • Patent number: 9530721
    Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: December 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Atsushi Nishikizawa, Tadatoshi Danno, Hiroyuki Nakamura, Osamu Soma, Akira Uemura
  • Publication number: 20160093557
    Abstract: A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
    Type: Application
    Filed: September 30, 2015
    Publication date: March 31, 2016
    Inventors: Atsushi NISHIKIZAWA, Tadatoshi DANNO, Hiroyuki NAKAMURA, Osamu SOMA, Akira UEMURA
  • Patent number: 8994159
    Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: March 31, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Hiroyuki Nakamura, Akira Muto, Nobuya Koike, Atsushi Nishikizawa, Yukihiro Sato, Katsuhiko Funatsu
  • Publication number: 20130127032
    Abstract: To prevent, in a resin-sealed type semiconductor package, generation of cracks in a die bonding material used for mounting of a semiconductor chip. A semiconductor chip is mounted over the upper surface of a die pad via a die bonding material, followed by sealing with an insulating resin. The top surface of the die pad to be brought into contact with the insulating resin is surface-roughened, while the bottom surface of the die pad and an outer lead portion are not surface-roughened.
    Type: Application
    Filed: January 14, 2013
    Publication date: May 23, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki NAKAMURA, Akira MUTO, Nobuya KOIKE, Atsushi NISHIKIZAWA, Yukihiro SATO, Katsuhiko FUNATSU