Patents by Inventor Atsushi Tsuboi

Atsushi Tsuboi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210375684
    Abstract: A method for manufacturing a semiconductor device includes forming a support on a side surface of a stack that extends from a substrate. The stack includes a second sacrificial film, plural first sacrificial films and plural silicon (Si)-containing films, wherein one first sacrificial film of the plural sacrificial films is stacked upon the second sacrificial film and the plural sacrificial films and the plural Si-containing films are alternately stacked upon one another, and at least a side of the second sacrificial film is not covered by the support, the one first sacrificial film and the substrate. The method further includes removing the second sacrificial film from the stack to form a space between the substrate and the one first sacrificial film and adjacent to the support, and filling the space with a dielectric film.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masaru SUGIMOTO, Hiroshi YANO, Yasushi KODASHIMA, Masanobu IGETA
  • Publication number: 20210376123
    Abstract: A method including depositing a dielectric film on a substrate including stacked structures with recessed portions formed on side surfaces of each of the stacked structures, wherein the dielectric film is deposited so that the stacked structures are covered at a thickness which is equal to or less than half a width of the recessed portions; filling a trench or trenches that are located between the stacked structures with a sacrificial film; etching the sacrificial film along the stacked structures; etching the dielectric film so that the dielectric film is etched more than the sacrificial film; removing the sacrificial film; after the removing of the sacrificial film, depositing a dielectric film to a thickness equal to or less than half the width of the recessed portions; and etching the deposited dielectric film, on a condition that the deposited dielectric film remains in the recessed portions.
    Type: Application
    Filed: May 25, 2021
    Publication date: December 2, 2021
    Applicant: Tokyo Electron Limited
    Inventors: Shimpei YAMAGUCHI, Atsushi TSUBOI, Atsushi ENDO, Masanobu IGETA, Masaru SUGIMOTO, Luis FERNANDEZ
  • Publication number: 20210168363
    Abstract: In a case where it is identified based on fisheye information that an input image is a fisheye image, a block position computing section computes the position of a processing target block relative to a fisheye center, and outputs, to a table selecting section, positional information representing the computed position. In a case where it is identified based on fisheye information that an input image is a fisheye image, the table selecting section selects, on the basis of positional information, an intra-prediction mode table according to the position of a processing target block from a plurality of intra-prediction mode tables, and outputs the selected intra-prediction mode table to a prediction image generating section.
    Type: Application
    Filed: April 3, 2019
    Publication date: June 3, 2021
    Applicant: SONY CORPORATION
    Inventors: Junichi MATSUMOTO, Atsushi TSUBOI, Hiromichi UENO
  • Patent number: 10461159
    Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hironobu Miyamoto, Tatsuo Nakayawa, Yasuhiro Okamoto, Atsushi Tsuboi
  • Patent number: 10249715
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: April 2, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Hironobu Miyamoto, Tatsuo Nakayama, Atsushi Tsuboi, Yasuhiro Okamoto, Hiroshi Kawaguchi
  • Publication number: 20180342589
    Abstract: Characteristics of a semiconductor device using a nitride semiconductor are improved. A semiconductor device of the present invention includes a buffer layer, a channel layer, a barrier layer, a mesa-type 2DEG dissolving layer, a source electrode, a drain electrode, a gate insulating film formed on the mesa-type 2DEG dissolving layer, and an overlying gate electrode. The gate insulating film of the semiconductor device includes a sputtered film formed on the mesa-type 2DEG dissolving layer and a CVD film formed on the sputtered film. The sputtered film is formed in a non-oxidizing atmosphere by a sputtering process using a target including an insulator. This makes it possible to reduce positive charge amount at a MOS interface and in gate insulating film and increase a threshold voltage, and thus improve normally-off characteristics.
    Type: Application
    Filed: April 30, 2018
    Publication date: November 29, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Hironobu MIYAMOTO, Tatsuo NAKAYAWA, Yasuhiro OKAMOTO, Atsushi TSUBOI
  • Publication number: 20180026099
    Abstract: Properties of a semiconductor device are improved. A semiconductor device is configured so as to include a voltage clamp layer, a channel underlayer, a channel layer, and a barrier layer, which are formed in order above a substrate, a trench that extends up to the middle of the channel layer while penetrating through the barrier layer, a gate electrode disposed within the trench with a gate insulating film in between, a source electrode and a drain electrode formed above the barrier layer on both sides of the gate electrode, and a fourth electrode electrically coupled to the voltage clamp layer. The fourth electrode is electrically isolated from the source electrode, and a voltage applied to the fourth electrode is different from a voltage applied to the source electrode. Consequently, threshold control can be performed. For example, a threshold of a MISFET can be increased.
    Type: Application
    Filed: May 25, 2017
    Publication date: January 25, 2018
    Applicant: Renesas Electronics Corporation
    Inventors: Hironobu MIYAMOTO, Tatsuo NAKAYAMA, Atsushi TSUBOI, Yasuhiro OKAMOTO, Hiroshi KAWAGUCHI
  • Patent number: 8934767
    Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.
    Type: Grant
    Filed: October 23, 2013
    Date of Patent: January 13, 2015
    Assignee: Sony Corporation
    Inventors: Ryoichi Nakashima, Atsushi Tsuboi
  • Publication number: 20140050467
    Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.
    Type: Application
    Filed: October 23, 2013
    Publication date: February 20, 2014
    Applicant: Sony Corporation
    Inventors: Ryoichi NAKASHIMA, Atsushi TSUBOI
  • Patent number: 8577219
    Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Sony Corporation
    Inventors: Ryoichi Nakashima, Atsushi Tsuboi
  • Publication number: 20120155849
    Abstract: An imaging apparatus includes a usable time calculation unit which calculates a usable time of a battery device having a secondary battery, wherein the usable time calculation unit measures an average power level while a component is performed at a predetermined operation mode, wherein the power consumption of the component is unknown in advance before the component is initially connected, and when power is supplied for the second and subsequent times while the component is continuously connected, the usable time calculation unit calculates the usable time of the battery device using the average power level and a current integration value which is an integration value of current flowing during charging and discharging of the battery device.
    Type: Application
    Filed: November 2, 2011
    Publication date: June 21, 2012
    Applicant: SONY CORPORATION
    Inventors: Ryoichi NAKASHIMA, Atsushi Tsuboi
  • Patent number: 7280008
    Abstract: In a fitting region for a SAW filter which includes langasite as its piezoelectric element, there are included an input side terminal electrode and an output side terminal electrode which are connected to an input terminal and to an output terminal of the SAW filter. To each of the terminal electrodes, at a position which is separated by just a predetermined distance from the fitting region of the SAW filter, there is connected a micro strip line which extends in mutually opposite directions along a direction which is parallel to the transmission direction of a frequency signal within the SAW filter. A slit is provided in the fitting region of the SAW filter and extends in a direction which intersects the transmission direction of the frequency signal within the SAW filter. A plurality of through holes are provided in the printed substrate and electrically connect together its surface and its rear surface which is grounded.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: October 9, 2007
    Assignees: Mitsubishi Materials Corporation, Matsushita Electric Industrial Co., Ltd.
    Inventors: Kunio Yamaguchi, Ryouhei Kimura, Atsushi Tsuboi, Kenyu Morozumi
  • Publication number: 20030104686
    Abstract: In a semiconductor device that includes a barrier film, an electrode pad on the barrier film, and a solder ball in the electrode pad, the electrode pad is prevented from exfoliating from the barrier film by a side wall film separating the solder ball from a boundary between the barrier film and the electrode pad.
    Type: Application
    Filed: November 15, 2002
    Publication date: June 5, 2003
    Applicant: NEC CORPORATION
    Inventor: Atsushi Tsuboi
  • Patent number: 6528881
    Abstract: In a semiconductor device that includes a barrier film, an electrode pad on the barrier film, and a solder ball on the electrode pad, the electrode pad is prevented from exfoliating from the barrier film by a side wall film separating the solder ball from a boundary between the barrier film and the electrode pad.
    Type: Grant
    Filed: August 17, 2000
    Date of Patent: March 4, 2003
    Assignee: NEC Corporation
    Inventor: Atsushi Tsuboi
  • Patent number: 6413841
    Abstract: First, a polysilicon film is formed on a gate oxide film. Next, a polysilicon oxide film is formed on the polysilicon film. Thereafter, the polysilicon film is thermally treated to allow a crystal grain in the polysilicon film to grow from the gate oxide film and the polysilicon oxide film. In a MOS type semiconductor device manufactured in this manner has a gate electrode formed of a plurality of laminated polycrystalline silicon layers each having substantially a single crystal grain in a thickness direction of the gate electrode.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: July 2, 2002
    Assignee: NEC Corporation
    Inventor: Atsushi Tsuboi
  • Publication number: 20020043124
    Abstract: A plastic gear is provided which includes a main body portion and a toothed portion. The main body portion is made of a synthetic resin containing reinforcement fibers. The toothed portion is made of a synthetic resin which is the same as the synthetic resin of which the main body portion is made except that it does not contain any reinforcement fibers. A method of producing such a plastic gear is also provided.
    Type: Application
    Filed: April 13, 2001
    Publication date: April 18, 2002
    Applicant: UNISIA JECS CORPORATION
    Inventors: Hirotaka Shiga, Atsushi Tsuboi, Yuzuru Morioka
  • Patent number: 5726098
    Abstract: An underlying interconnection is formed on a semiconductor substrate, and an interlayer insulating film is formed on the semiconductor substrate and the underlying interconnection. A metal film is deposited on the interlayer insulating film, and is patterned in an interconnection pattern, and a first opening for connecting the metal film to the underlying interconnection is patterned, thereby forming an overlying interconnection. Then, a protection film is formed so as to cover the surfaces of the overlying interconnection and the interlayer insulating film. Next, a photoresist film is formed on the protection film, and is patterned to provide a second opening larger than the first opening in the protection film above the first opening and provide a third opening in a pad-portion forming region on the overlying interconnection. At the same time, with the overlying interconnection as a mask, the interlayer insulating film is selectively etched out to form a through hole.
    Type: Grant
    Filed: September 21, 1995
    Date of Patent: March 10, 1998
    Assignee: NEC Corporation
    Inventor: Atsushi Tsuboi