Patents by Inventor Attila Mekis

Attila Mekis has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240369772
    Abstract: Certain embodiments of the present disclosure are directed towards an optical assembly such as a wavelength multiplexers/demultiplexers (MDM). One example optical assembly generally includes: one or more wavelength filters configured to separate a plurality of wavelengths of an optical signal into respective optical signals; and a lens array comprising a first angled facet configured to reflect the optical signal to the one or more wavelength filters, wherein the lens array is configured to receive one or more of the respective optical signals from the one or more wavelength filters and focus the one or more of the respective optical signals before reaching an optical interface for a photonic chip.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 7, 2024
    Inventors: Roman BRUCK, Shawn X. WANG, Attila MEKIS
  • Publication number: 20240356656
    Abstract: The present disclosure describes photodetectors with multiple inputs and methods of operating photodetectors with multiple inputs. An apparatus includes a substrate, an optical absorber, and an optical device. The optical absorber is positioned on the substrate. The optical absorber includes a first portion and a second portion coupled to the first portion along a line. The optical device produces a first optical signal and a second optical signal based on a received optical signal and directs the first optical signal through the first portion of the optical absorber in a direction substantially parallel to the line. The optical device also directs the second optical signal through the second portion of the optical absorber in the direction substantially parallel to the line.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Inventors: Rajat SHARMA, Fatemeh REZAEIFAR BAYAT, Attila MEKIS, Gianlorenzo MASINI
  • Publication number: 20240353729
    Abstract: The present disclosure describes photodetectors with multiple inputs and methods of operating photodetectors with multiple inputs. An apparatus includes a substrate, an optical absorber, an optical device, and a tuner. The optical absorber is positioned on the substrate. The optical device produces a first optical signal and a second optical signal from an optical signal received at a first port of the optical device and directs the first optical signal and the second optical signal to the optical absorber. The tuner adjusts a first phase of the first optical signal and a second phase of the second optical signal such that a reflection of the first optical signal from the optical absorber destructively interferes with a reflection of the second optical signal from the optical absorber at the first port.
    Type: Application
    Filed: April 18, 2023
    Publication date: October 24, 2024
    Inventors: Rajat SHARMA, Donald J. ADAMS, Attila MEKIS, Gianlorenzo MASINI
  • Publication number: 20240243214
    Abstract: A photodetector and method of making a photodetector are disclosed. An apparatus includes a semiconductor disk, a first doped region, and a first absorption region. The first doped region is disposed within the semiconductor disk such that the first doped region extends across a center of the semiconductor disk. The first doped region has a first doping type. The first absorption region is disposed on the first doped region such that a portion of the first doped region is positioned between the center of the semiconductor disk and the first absorption region along a radius of the semiconductor disk. The first absorption region includes a second doped region with a second doping type different from the first doping type. The first absorption region is arranged to absorb an optical signal as the optical signal travels along an inner circumference of the semiconductor disk.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Inventors: Rajat SHARMA, Attila MEKIS, Gianlorenzo MASINI
  • Publication number: 20240241309
    Abstract: Embodiments herein described an optical system for testing the bandwidth of a photodiode (PD) in a photonic integrated circuit (PIC). In one embodiment, a first optical signal is provided to bias one or more PDs in the PIC which generate a DC bias (e.g., DC voltage) across the PD whose bandwidth is being tested. A second optical signal is directed to the PD being tested, thereby generating an AC signal. The second optical signal can be a tunable optical signal where its frequency/wavelength is varied to test the bandwidth of the PD. The AC signal generated by the PD being tested is passed through a heating element (e.g., a resistor) which generates heat. This heat is then measured by an interferometer. The output of the interferometer can be correlated to a bandwidth of the PD.
    Type: Application
    Filed: January 18, 2023
    Publication date: July 18, 2024
    Inventors: Attila MEKIS, Gianlorenzo MASINI
  • Patent number: 12025831
    Abstract: End-face coupling structures within an electrical backend are provided via photonic integrated circuit (PIC), comprising: a first plurality of spacer layers; a second plurality of etch-stop layers, wherein each etch-stop layer of the second plurality of etch-stop layers is located between two spacer layers of the first plurality of spacer layers; and an optical coupler comprising a plurality of waveguides arranged as a waveguide array configured to receive an optical signal in a direction of travel, wherein each waveguide of the plurality of waveguides is located at a layer interface defined between an etch-stop layer and a spacer layer. Portions of the PIC can be formed by depositing layers of spacer and etch-stop materials in which cavities are formed to define the waveguides when the waveguide material is deposited or interconnects when a metal is deposited therein.
    Type: Grant
    Filed: April 7, 2023
    Date of Patent: July 2, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Roman Bruck, Thierry J. Pinguet, Attila Mekis
  • Publication number: 20240194813
    Abstract: A photodetector includes a substrate, an absorber, a first doped region, and a second doped region. The absorber includes a first region and a second region that is more heavily doped than the first region. The first doped region is positioned on the substrate such that the first doped region contacts the second region of the absorber. A portion of the first doped region is positioned between the absorber and the substrate. The second doped region is positioned on the substrate such that the second doped region contacts the first region of the absorber rather than the second region of the absorber. A portion of the second doped region is positioned between the absorber and the substrate. The portion of the second doped region extends across a majority of a width of the absorber.
    Type: Application
    Filed: December 8, 2022
    Publication date: June 13, 2024
    Inventors: Kam Yan HON, Fatemeh REZAEIFAR BAYAT, Attila MEKIS, Gianlorenzo MASINI
  • Publication number: 20240077672
    Abstract: Embodiments include a photonic device with a compensation structure. The photonic device includes a waveguide with a refractive index which changes according to the thermo-optic effect as a temperature of the photonic device fluctuates. The compensation structure is positioned on the photonic device to counteract or otherwise alter the thermo-optic effect on the refractive index of the waveguide in order to prevent malfunctions of the photonic device.
    Type: Application
    Filed: November 10, 2023
    Publication date: March 7, 2024
    Inventors: Subal SAHNI, Kamal V. KARIMANAL, Gianlorenzo MASINI, Attila MEKIS, Roman BRUCK
  • Publication number: 20240038920
    Abstract: A photodetector includes a substrate, a first optical absorber, and a second optical absorber. The first optical absorber is disposed in the substrate along a direction of propagation of an optical signal through the substrate. The first optical absorber is offset in the substrate according to an offset of the optical signal in a direction orthogonal to the direction of propagation. The second optical absorber is disposed in the substrate along the direction of propagation of the optical signal. The second optical absorber is offset in the substrate according to the offset of the optical signal in the direction orthogonal to the direction of propagation.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Fatemeh REZAEIFAR BAYAT, Kam Yan HON, Attila MEKIS, Gianlorenzo MASINI
  • Publication number: 20240004260
    Abstract: Methods and systems for a vertical junction high-speed phase modulator are disclosed and may include a semiconductor device having a semiconductor waveguide including a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section. The semiconductor device has a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib and slab sections. The rib section may be either fully n-doped or p-doped in each cross-section along the semiconductor waveguide. Electrical connection to the p-doped and n-doped material may be enabled by forming contacts on the raised ridges, and electrical connection may be provided to the rib section from one of the contacts via periodically arranged sections of the semiconductor waveguide, where a cross-section of both the rib section and the slab section in the periodically arranged sections may be fully n-doped or fully p-doped.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Inventors: Attila MEKIS, Subal SAHNI, Yannick DE KONINCK, Gianlorenzo MASINI, Faezeh GHOLAMI
  • Patent number: 11860412
    Abstract: Embodiments include a photonic device with a compensation structure. The photonic device includes a waveguide with a refractive index which changes according to the thermo-optic effect as a temperature of the photonic device fluctuates. The compensation structure is positioned on the photonic device to counteract or otherwise alter the thermo-optic effect on the refractive index of the waveguide in order to prevent malfunctions of the photonic device.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: January 2, 2024
    Assignee: Cisco Technology, Inc.
    Inventors: Subal Sahni, Kamal V. Karimanal, Gianlorenzo Masini, Attila Mekis, Roman Bruck
  • Patent number: 11822136
    Abstract: The present disclosure provides for two-dimensional mode matching by receiving an optical signal traveling in a first direction; and scattering the optical signal according lto a scattering strength that progressively changes in the first direction. In various embodiments, the scattering strength progressively changes by increasing or decreasing in the first direction. A plurality of scatterers disposed in a path of the optical signal change in widths that progressively increase or decrease along the first direction. In various embodiments, a second optical signal is received in the grating coupler from a second direction; and is scattered into a surface of a photonic chip via a grating coupler. In some embodiments, the second direction is perpendicular to the first direction.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: November 21, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Roman Bruck, Attila Mekis
  • Patent number: 11796888
    Abstract: Methods and systems for a vertical junction high-speed phase modulator are disclosed and may include a semiconductor device having a semiconductor waveguide including a slab section, a rib section extending above the slab section, and raised ridges extending above the slab section on both sides of the rib section. The semiconductor device has a vertical pn junction with p-doped material and n-doped material arranged vertically with respect to each other in the rib and slab sections. The rib section may be either fully n-doped or p-doped in each cross-section along the semiconductor waveguide. Electrical connection to the p-doped and n-doped material may be enabled by forming contacts on the raised ridges, and electrical connection may be provided to the rib section from one of the contacts via periodically arranged sections of the semiconductor waveguide, where a cross-section of both the rib section and the slab section in the periodically arranged sections may be fully n-doped or fully p-doped.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: October 24, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Attila Mekis, Subal Sahni, Yannick De Koninck, Gianlorenzo Masini, Faezeh Gholami
  • Publication number: 20230266545
    Abstract: According to an embodiment, an apparatus includes a first grating and a second grating in a stack with the first grating. The first grating includes a first plurality of scatterers in a first two-dimensional (2D) arrangement. The second grating includes a second plurality of scatterers in a second 2D arrangement. The first grating and the second grating are arranged to redirect a first optical signal and a second optical signal traveling through the stack. The first optical signal enters the stack in a first direction, and the second optical signal enters the stack in a second direction different from the first direction. Each of the second plurality of scatterers is offset from a corresponding scatterer of the first plurality of scatterers in a third direction different from the first and second directions. Other embodiments include a method performed by the apparatus.
    Type: Application
    Filed: February 24, 2022
    Publication date: August 24, 2023
    Inventors: Roman BRUCK, Attila MEKIS
  • Patent number: 11735574
    Abstract: Methods and systems for selectively illuminated integrated photodetectors with configured launching and adaptive junction profile for bandwidth improvement may include a photonic chip comprising an input waveguide and a photodiode. The photodiode comprises an absorbing region with a p-doped region on a first side of the absorbing region and an n-doped region on a second side of the absorbing region. An optical signal is received in the absorbing region via the input waveguide, which is offset to one side of a center axis of the absorbing region; an electrical signal is generated based on the received optical signal. The first side of the absorbing region may be p-doped. P-doped and n-doped regions may alternate on the first and second sides of the absorbing region along the length of the photodiode. The absorbing region may comprise germanium, silicon, silicon/germanium, or similar material that absorbs light of a desired wavelength.
    Type: Grant
    Filed: June 16, 2021
    Date of Patent: August 22, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Kam-Yan Hon, Subal Sahni, Gianlorenzo Masini, Attila Mekis
  • Publication number: 20230244031
    Abstract: End-face coupling structures within an electrical backend are provided via photonic integrated circuit (PIC), comprising: a first plurality of spacer layers; a second plurality of etch-stop layers, wherein each etch-stop layer of the second plurality of etch-stop layers is located between two spacer layers of the first plurality of spacer layers; and an optical coupler comprising a plurality of waveguides arranged as a waveguide array configured to receive an optical signal in a direction of travel, wherein each waveguide of the plurality of waveguides is located at a layer interface defined between an etch-stop layer and a spacer layer. Portions of the PIC can be formed by depositing layers of spacer and etch-stop materials in which cavities are formed to define the waveguides when the waveguide material is deposited or interconnects when a metal is deposited therein.
    Type: Application
    Filed: April 7, 2023
    Publication date: August 3, 2023
    Inventors: Roman BRUCK, Thierry J. PINGUET, Attila MEKIS
  • Patent number: 11675128
    Abstract: End-face coupling structures within an electrical backend are provided via photonic integrated circuit (PIC), comprising: a first plurality of spacer layers; a second plurality of etch-stop layers, wherein each etch-stop layer of the second plurality of etch-stop layers is located between two spacer layers of the first plurality of spacer layers; and an optical coupler comprising a plurality of waveguides arranged as a waveguide array configured to receive an optical signal in a direction of travel, wherein each waveguide of the plurality of waveguides is located at a layer interface defined between an etch-stop layer and a spacer layer. Portions of the PIC can be formed by depositing layers of spacer and etch-stop materials in which cavities are formed to define the waveguides when the waveguide material is deposited or interconnects when a metal is deposited therein.
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: June 13, 2023
    Assignee: Cisco Technology, Inc.
    Inventors: Roman Bruck, Thierry J. Pinguet, Attila Mekis
  • Patent number: 11438065
    Abstract: Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses. The devices may be fabricated on semiconductor-on-insulator (SOI) wafers utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: September 6, 2022
    Assignee: Luxtera, Inc.
    Inventors: Attila Mekis, Peter DeDobbelaere, Kosei Yokoyama, Sherif Abdalla, Steffen Gloeckner, John Guckenberger, Thierry Pinguet, Gianlorenzo Masini, Daniel Kucharski
  • Patent number: 11424837
    Abstract: Methods and systems for large silicon photonic interposers by stitching are disclosed and may include, in an optical communication system including a silicon photonic interposer, where the interposer includes a plurality of reticle sections: communicating an optical signal between first and second reticle sections utilizing a waveguide. The waveguide may include a taper region at a boundary between the two reticle sections, the taper region expanding an optical mode of the communicated optical signal prior to the boundary and narrowing the optical mode after the boundary. A continuous wave (CW) optical signal may be received in a first of the reticle sections from an optical source external to the interposer. The CW optical signal may be received in the interposer from an optical source assembly coupled to a grating coupler in the first of the reticle sections in the silicon photonic interposer.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: August 23, 2022
    Assignee: Cisco Technology, INC
    Inventors: Peter De Dobbelaere, Attila Mekis, Gianlorenzo Masini
  • Publication number: 20220260775
    Abstract: End-face coupling structures within an electrical backend are provided via photonic integrated circuit (PIC), comprising: a first plurality of spacer layers; a second plurality of etch-stop layers, wherein each etch-stop layer of the second plurality of etch-stop layers is located between two spacer layers of the first plurality of spacer layers; and an optical coupler comprising a plurality of waveguides arranged as a waveguide array configured to receive an optical signal in a direction of travel, wherein each waveguide of the plurality of waveguides is located at a layer interface defined between an etch-stop layer and a spacer layer. Portions of the PIC can be formed by depositing layers of spacer and etch-stop materials in which cavities are formed to define the waveguides when the waveguide material is deposited or interconnects when a metal is deposited therein.
    Type: Application
    Filed: February 18, 2021
    Publication date: August 18, 2022
    Inventors: Roman BRUCK, Thierry J. PINGUET, Attila MEKIS