Patents by Inventor Atul Ghia

Atul Ghia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7480361
    Abstract: Method and apparatus for phase lock detection is described. More particularly, a phase lock detection circuit (20) includes a synchronization circuit (23) coupled to receive a reference signal (31) and configured to provide a derivative signal (32). A phase lock detector (21) is coupled to receive the reference signal (31) and the derivative signal (32) and is configured to provide a cycle lock signal (24) indicating whether a phase lock exists within a lock window (57) for a clock cycle.
    Type: Grant
    Filed: July 12, 2004
    Date of Patent: January 20, 2009
    Assignee: Xilinx, Inc.
    Inventors: Qi Zhang, Atul Ghia
  • Publication number: 20070013428
    Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
    Type: Application
    Filed: August 29, 2006
    Publication date: January 18, 2007
    Applicant: Xilinx, Inc.
    Inventors: Vasisht Vadi, Steven Young, Atul Ghia, Adebabay Bekele, Suresh Menon
  • Publication number: 20060290403
    Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 28, 2006
    Applicant: Xilinx, Inc.
    Inventors: Vasisht Vadi, Steven Young, Atul Ghia, Adebabay Bekele, Suresh Menon
  • Publication number: 20060290402
    Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
    Type: Application
    Filed: August 29, 2006
    Publication date: December 28, 2006
    Applicant: Xilinx, Inc.
    Inventors: Vasisht Vadi, Steven Young, Atul Ghia, Adebabay Bekele, Suresh Menon
  • Patent number: 7091890
    Abstract: A serializer-deserializer instantiated in configurable logic of an integrated circuit is described. The serializer-deserializer includes an input deserializer and an output serializer, which may be commonly coupled via an input/output pad. Each of the serializer and deserializer may be configured for an operating mode selected from a Single Data Rate mode and a Double Data Rate mode. The serializer-deserializer may be used as part of a synchronous interface.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: August 15, 2006
    Assignee: Xilinx, Inc.
    Inventors: Paul T. Sasaki, Jason R. Bergendahl, Atul Ghia, Hassan Bazargan, Ketan Sodha, Jian Tan, Qi Zhang, Suresh Menon
  • Patent number: 6985096
    Abstract: Method and apparatus for a bimodal serial to parallel converter is provided. A first stage of registers is clocked responsive to a clock signal, such as a forwarded clock signal of a synchronous interface. The first stage of registers is configurable in either a single serial shift chain or two serial shift chains. The former configuration is for Single Data Rate (“SDR”) data, and the latter configuration is for Double Data Rate (“DDR”) data. A bitslip controller is configured to provide a control select signal to selection circuitry. For DDR operation, the control signal is for selecting respective portions of outputs from the two serial shift chains for providing to a second stage of registers. For DDR operation, the second stage of registers is alternatively clocked responsive to a divided down version of the clock signal and another divided down version of the clock signal which is periodically stopped.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: January 10, 2006
    Assignee: Xilinx, Inc.
    Inventors: Paul T. Sasaki, Jason R. Bergendahl, Atul Ghia, Jian Tan
  • Publication number: 20050242867
    Abstract: A system for distributing a small signal differential signal to a circuit element. The system includes: a first converter configured to convert a first small signal differential signal to a first two phase full CMOS differential signal for input into the differential multiplexer; and a programmable driver circuit configured to boost an output current of the programmable driver circuit at selected frequencies and to convert two phase full CMOS differential signal outputs of the differential multiplexer to a second small signal differential signal.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Applicant: Xilinx, Inc.
    Inventors: Atul Ghia, Adebabay Bekele
  • Publication number: 20050242866
    Abstract: A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Applicant: Xilinx, Inc.
    Inventors: Vasisht Vadi, Steven Young, Atul Ghia, Adebabay Bekele, Suresh Menon
  • Publication number: 20050242865
    Abstract: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Applicant: Xilinx, Inc.
    Inventors: Vasisht Vadi, Steven Young, Atul Ghia, Adebabay Bekele, Suresh Menon