Patents by Inventor Aubrey Deene Ogden

Aubrey Deene Ogden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6430190
    Abstract: A router coupled to a plurality of networks receives a data packet from a first one of the networks and routes the data packet to a second one of the networks. The data packet includes a first portion having a destination network address. The router receives a first portion of the data packet, and the first portion of the data packet includes a destination network address. The destination network address of the data packet is asserted to a content addressable memory (“CAM”), where the CAM has stored routing information, while the first packet is not yet fully received from the first network. The CAM identifies one of the networks coupled to the router, in response to the destination network address being in the CAM, while the router is still receiving a remaining portion of the data packet. After identification of the destination network the data packet is routed to the destination network.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: August 6, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: Alexander Dankwart Essbaum, Aubrey Deene Ogden
  • Patent number: 6236658
    Abstract: In a router coupled to a number of networks, a data packet is received from a first one of the networks and routed to a second one of the networks. The data packet includes a first portion having a destination network address. The destination network address for the data packet is input to a content addressable memory (“CAM”) while the router is still receiving at least a portion of the data packet, so that the CAM, having network address information stored therein, identifies one of the networks coupled to the router and corresponding to the destination address of the data packet while the router is still receiving at least a portion of the data packet.
    Type: Grant
    Filed: November 21, 1997
    Date of Patent: May 22, 2001
    Assignee: Cisco Technology, Inc.
    Inventors: Alexander Dankwart Essbaum, Aubrey Deene Ogden
  • Patent number: 5978896
    Abstract: A method and system for increased instruction dispatch efficiency in a superscalar processor system having an instruction queue for receiving a group of instructions in an application specified sequential order and an instruction dispatch unit for dispatching instructions from an associated instruction buffer to multiple execution units on an opportunistic basis. The dispatch status of instructions within the associated instruction buffer is periodically determined and, in response to a dispatch of the instructions at the beginning of the instruction buffer, the remaining instructions are shifted within the instruction buffer in the application specified sequential order and a partial group of instructions are loaded into the instruction buffer from the instruction queue utilizing a selectively controlled multiplex circuit. In this manner additional instructions may be dispatched to available execution units without requiring a previous group of instructions to be dispatched completely.
    Type: Grant
    Filed: August 12, 1994
    Date of Patent: November 2, 1999
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Chin-Cheng Kau, David Steven Levitan, Aubrey Deene Ogden
  • Patent number: 5898882
    Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units for execution and placement of results thereof within specified general purpose registers. Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers are provided and each time an instruction is dispatched to an available execution unit, a particular one of the intermediate storage buffers is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register or a designated alternate general purpose register.
    Type: Grant
    Filed: January 8, 1993
    Date of Patent: April 27, 1999
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Chin-Cheng Kau, Aubrey Deene Ogden, Ali Asghar Poursepanj, Paul Kang-Guo Tu, Donald Emil Waldecker
  • Patent number: 5764942
    Abstract: The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
    Type: Grant
    Filed: August 12, 1996
    Date of Patent: June 9, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Chin-Cheng Kau, Aubrey Deene Ogden, Ali Asghar Poursepanj, Paul Kang-Guo Tu, Donald Emil Waldecker
  • Patent number: 5764969
    Abstract: A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execution of such an instruction is initiated an enable special access (ESA) instruction is executed as an entry point to that instruction or group of instructions. A portion of the machine state register for the data processing system is stored and the machine state register is then modified as follows: a problem bit is set, changing the execution privilege state to "supervisor;" external interrupts are disabled; and access privilege state bit is set; and, a special access mode bit is set, allowing execution of special instructions. The instructions which execute the selected privileged operations within the protected memory space are then executed.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: June 9, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Albert J. Loper, Soummya Mallick, Aubrey Deene Ogden, John Victor Sell
  • Patent number: 5758141
    Abstract: A method and system for permitting the selective support of non-architected instructions within a superscalar processor system. A special access bit within the system machine state register is provided and set in response to each initiation of an application during which execution of non-architected instructions is desired. Thereafter, each time a non-architected instruction is decoded the status of the special access bit is determined. The non-architected instruction is executed in response to a set state of the special access bit. The illegal instruction program interrupt is issued in response to an attempted execution of a non-architected instruction if the special access bit is not set. In this manner, for example, complex instruction set computing (CISC) instructions may be selectively enabled for execution within a reduced instruction set computing (RISC) data processing system while maintaining full architectural compliance with the reduced instruction set computing (RISC) instructions.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: May 26, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Albert J. Loper, Soummya Mallick, Aubrey Deene Ogden, John Victor Sell
  • Patent number: 5732005
    Abstract: A single-precision floating-point register array for a floating-point execution unit that performs double-precision operations by emulation is provided. The register array comprises a plurality of single-precision floating-point registers and a storage device that stores one or more status bits in association with each of the plurality of registers; the status bits associated with each register indicate either that the associated data register contains single-precision or integer data, or that the data for the associated register is contained in an emulated register in memory that is mapped to the associated register. When a register is a source for an operation, the status bits associated with the register are checked and the required operand data for that register is read from the register or from an emulated register mapped to that register, as a function of the state of the status bits.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: March 24, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Tai Dinh Ngo, Aubrey Deene Ogden, Michael Putrino, Johm Victor Sell
  • Patent number: 5715420
    Abstract: A method and system for efficient memory management in a data processing system which utilizes a memory management unit to translate effective addresses into real addresses within a translation lookaside buffer is disclosed. During a first mode of operation a selected number of effective address identifiers are stored in the translation lookaside buffer. In association with each virtual address identifier is a corresponding real address entry for a single memory block wherein selected virtual addresses may be translated into corresponding real addresses utilizing the translation lookaside buffer.
    Type: Grant
    Filed: February 10, 1995
    Date of Patent: February 3, 1998
    Assignee: International Business Machines Corporation
    Inventors: James Allan Kahle, Albert J. Loper, Aubrey Deene Ogden, John Victor Sell, Gregory L. Limes
  • Patent number: 5655141
    Abstract: A processing system and method of operation are provided. At least one execution unit processes information of a register in response to an instruction specifying the register. Each of multiple control units selectively allocates a respective one of multiple buffers to store the information in response to the instruction.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: August 5, 1997
    Assignee: International Business Machines Corporation
    Inventors: Aubrey Deene Ogden, Neil Ray Vanderschaaf